AT7911E
3. Pin Description
Table 2. Pin description
5V 0.5V
max. output
current [mA]
3.3V 0.3V
Signal Name(1)(3) Type(2)(4)
Function
load [pF]
max. output
current [mA]
HSEL*
HRD*
HWR*
I
I
I
Select host interface
host interface read strobe
host interface write strobe
AT7911E register address lines. These address lines will be
used to access (address) the AT7911E registers.
HADR(7:0)
I
HDATA(31:0)
IO/Z
AT7911E data
3
3
3
1.5
1.5
1.5
50
50
50
host acknowledge. The AT7911E deasserts this output to
add waitstates to an AT7911E access. After AT7911E is
ready this output will be asserted.
HACK
O/Z
HINTR*
O/Z
I
host interrupt request line
Address. The binary value of these lines will be compared
with the value of the ID lines.
SMCSADR(3:0 )
ID lines: offers possibility to use sixteen AT7911E within one
HSEL*
SMCSID(3:0)
HOSTBIGE
BOOTLINK
I
I
I
0: host I/F Little Endian
1: host I/F Big Endian
0: control by host
1: control by link
Communication memory select lines. These pins are
asserted as chip selects for the corresponding banks of the
communication memory.
CMCS(1:0)*
O/Z
6
3
25
Communication memory read strobe. This pin is asserted
when the AT7911E reads data from memory.
CMRD*
CMWR*
O/Z
O/Z
O/Z
IOZ
6
6
6
3
3
3
25
25
25
25
Communication memory write strobe. This pin is asserted
when the AT7911E writes to data memory.
Communication memory address. The AT7911E outputs an
address on these pins.
CMADR(15:0)
CMDATA(31:0)
3
Communication memory data. The AT7911E inputs and
outputs data from and to com. memory on these pins.
1.5
COCI
I
Communication interface 'occupied' input signal
Communication interface 'occupied' output signal
COCO
O
3
1.5
50
Communication interface arbitration master input signal
CAM
I
1: master
0: slave
CPUR*
SES(3:0)*
LDI1
O
O
I
CPU Reset Signal (can be used as user defined flag)
Specific External Signals (can be used as user defined flags)
Link Data Input channel 1
3
3
1.5
1.5
50
50
LSI1
I
Link Strobe Input channel 1
LDO1
O
Link Data Output channel 1
12
6
25
5
7737B–AERO–05/08
ATMEL [ ATMEL ]
