AT7911E
3. Pin Description
Table 2.
Pin description
5V
±
0.5V
Signal Name
HSEL*
HRD*
HWR*
HADR(7:0)
HDATA(31:0)
HACK
HINTR*
SMCSADR(3:0 )
SMCSID(3:0)
(1)(3)
3.3V
±
0.3V
max. output
current [mA]
load [pF]
Type
I
I
I
I
(2)(4)
Function
max. output
current [mA]
Select host interface
host interface read strobe
host interface write strobe
AT7911E register address lines. These address lines will be
used to access (address) the AT7911E registers.
AT7911E data
host acknowledge. The AT7911E deasserts this output to
add waitstates to an AT7911E access. After AT7911E is
ready this output will be asserted.
host interrupt request line
Address. The binary value of these lines will be compared
with the value of the ID lines.
ID lines: offers possibility to use sixteen AT7911E within one
HSEL*
0: host I/F Little Endian
1: host I/F Big Endian
0: control by host
1: control by link
Communication memory select lines. These pins are
asserted as chip selects for the corresponding banks of the
communication memory.
Communication memory read strobe. This pin is asserted
when the AT7911E reads data from memory.
Communication memory write strobe. This pin is asserted
when the AT7911E writes to data memory.
Communication memory address. The AT7911E outputs an
address on these pins.
Communication memory data. The AT7911E inputs and
outputs data from and to com. memory on these pins.
Communication interface 'occupied' input signal
Communication interface 'occupied' output signal
Communication interface arbitration master input signal
1: master
0: slave
CPU Reset Signal (can be used as user defined flag)
Specific External Signals (can be used as user defined flags)
Link Data Input channel 1
Link Strobe Input channel 1
Link Data Output channel 1
12
6
25
3
3
1.5
1.5
50
50
3
1.5
50
6
3
25
3
3
3
1.5
1.5
1.5
50
50
50
IO/Z
O/Z
O/Z
I
I
HOSTBIGE
I
BOOTLINK
I
CMCS(1:0)*
O/Z
CMRD*
CMWR*
CMADR(15:0)
CMDATA(31:0)
COCI
COCO
CAM
CPUR*
SES(3:0)*
LDI1
LSI1
LDO1
O/Z
O/Z
O/Z
IOZ
I
O
I
O
O
I
I
O
6
6
6
3
3
3
3
1.5
25
25
25
25
5
7737B–AERO–05/08