AT7911E
9. PLL Filter
The AT7911E embeds a PLL to generate its internal clock reference. The PLLOUT pin of the
PLL is the output of the AT7911E that allows connection of the external filter of the PLL. The fol-
lowing figure presents the connection of the PLL filter.
Figure 9-1. PLL filter
AT7911E
Table 9-1.
PLL filter recommended components
VCC = +5V 0.5V
VCC = +3.3V 0.3V
R1
C1
C2
1,8 kΩ 5%, ¼W
33pF, 5%
R1
C1
C2
2,0 kΩ 5%, ¼W
33pF, 5%
820pF, 5%
760pF, 5%
10. Power Supply
To achieve its fast cycle time, the AT7911E is designed with high speed drivers on output pins.
Large peak currents may pass through a circuit board’s ground and power lines, especially when
many output drivers are simultaneously charging or discharging their load capacitances. These
transient currents can cause disturbances on the power and ground lines. To minimize these
effects, the AT7911E provides separate supply pins for its internal logic and for its external
drivers.
All GND pins should have a low impedance path to ground. A ground plane is required in
AT7911E systems to reduce this impedance, minimizing noise.
The VCC pins should be bypassed to the ground plane using approximately 10 high-frequency
capacitors (0.1 F ceramic). Keep each capacitor’s lead and trace length to the pins as short as
possible. This low inductive path provides the AT7911E with the peak currents required when its
output drivers switch. The capacitors’ ground leads should also be short and connect directly to
the ground plane. This provides a low impedance return path for the load capacitance of the
AT7911E output drivers.
The following pins must have a capacitor: 20, 78, 129, and 155. The remaining capacitors
should be distributed equally around the AT7911E.
15
7737B–AERO–05/08
ATMEL [ ATMEL ]
