29. Preload of Registered Outputs
The ATF750C(L)’s registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level on the I/O pin will force the regis-
ter high; a VIL will force it low, independent of the output polarity. The PRELOAD state is entered
by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock
term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin
.
Level Forced on Registered
Output Pin during Preload Cycle
Select Pin
State
Register #0 State
after Cycle
Register #1 State
after Cycle
VIH
VIL
VIH
VIL
Low
Low
High
High
High
Low
X
X
X
High
Low
X
14
ATF750C(L)
0776L–PLD–11/08
ATMEL [ ATMEL ]
