欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962-0720101MLA 参数 Datasheet PDF下载

5962-0720101MLA图片预览
型号: 5962-0720101MLA
PDF下载: 下载PDF文件 查看货源
内容描述: 高速复杂可编程逻辑器件 [High-speed Complex Programmable Logic Device]
分类和应用: 可编程逻辑器件
文件页数/大小: 25 页 / 490 K
品牌: ATMEL [ ATMEL ]
 浏览型号5962-0720101MLA的Datasheet PDF文件第8页浏览型号5962-0720101MLA的Datasheet PDF文件第9页浏览型号5962-0720101MLA的Datasheet PDF文件第10页浏览型号5962-0720101MLA的Datasheet PDF文件第11页浏览型号5962-0720101MLA的Datasheet PDF文件第13页浏览型号5962-0720101MLA的Datasheet PDF文件第14页浏览型号5962-0720101MLA的Datasheet PDF文件第15页浏览型号5962-0720101MLA的Datasheet PDF文件第16页  
23. Using the ATF750C’s Many Advanced Features  
The ATF750C(L)’s advanced flexibility packs more usable gates into 24 pins than any other logic  
device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced  
features:  
Selectable D- and T-type Registers  
Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the T-  
type configuration, JK and SR flip-flops are also easily created. These options allow more  
efficient product term usage.  
Selectable Asynchronous Clocks  
Each of the ATF750C(L)’s flip-flops may be clocked by its own clock product term or directly  
from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same  
clock. Buried state machines, counters and registers can all coexist in one device while  
running on separate clocks. Individual flip-flop clock source selection further allows mixing  
higher performance pin clocking and flexible product term clocking within one design.  
A Full Bank of Ten More Registers  
The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register  
has its own sum term, its own reset term and its own clock term.  
Independent I/O Pin and Feedback Paths  
Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its  
own feedback terms into the array as well. This feature, combined with individual product  
terms for each I/O’s output enable, facilitates true bi-directional I/O design.  
24. Synchronous Preset and Asynchronous Reset  
One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate  
input signals to cause the internal clocks to go to a high state must be received during a syn-  
chronous preset. Appropriate setup and hold times must be met, as shown in the switching  
waveform diagram.  
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and  
slave halves of the flip-flops are reset when the input signals received force the internal resets  
high.  
25. Software Support  
All family members of the ATF750C(L) can be designed with Atmel®-WinCUPL.  
Additionally, the ATF750C may be programmed to perform the ATV750(L) functional subset (no  
T-type flip-flops, pin clocking or D/T2 feedback) using the ATV750 JEDEC file. In this case, the  
ATF750C becomes a direct replacement or speed upgrade for the ATV750. The ATF750C is a  
direct replacement for the ATV750(L) and the ATV750B(L).  
12  
ATF750C(L)  
0776L–PLD–11/08  
 复制成功!