Instruction Set
TSC695FL instructions fall into six functional categories: load/store, arithmetic/logi-
cal/shift, control transfer, read/write control register, floating-point, and miscellaneous.
Please refer to SPARC V7 Instruction-set Manual.
Note:
The execution of IFLUSH will cause an illegal instruction trap.
On-chip Peripherals
Memory Interface
Table 1.
Memory Mapping
Memory Contents
Start Address
Size (bytes)
Data Size and Parity Options
8-bit mode
Boot PROM
0x 0000 0000
128K
→
16M
40-bit mode
8-bit mode
Extended PROM
Exchange Memory
System Registers
RAM (8 blocks)
Extended RAM
I/O Area 0
I/O Area 1
I/O Area 2
I/O Area 3
Extended I/O Area
Extended General
0x 0100 0000
0x 01F0 0000
0x 01F8 0000
0x 0200 0000
0x 0400 0000
0x 1000 0000
0x 1100 0000
0x 1200 0000
0x 1300 0000
0x 1400 0000
0x 8000 0000
Max: 15M
4K
→
512K
512K (124 used)
8*32K
→
8*4M
Max: 192M
0
→
16M
0
→
16M
0
→
16M
0
→
16M
Max: 1728M
Max: 2G
Parity option/-All data sizes allowed
No parity/-All data sizes allowed
Parity + EDAC option/-All data sizes allowed
40-bit mode
No parity/-No EDAC/-Only byte write
Parity + EDAC mandatory/-Only word write
No parity/-No EDAC/-Only byte write
Parity + EDAC mandatory/-Only word write
The TSC695FL is designed to allow easy interfacing to internal/external memory
resources.
Parity + EDAC option/-Only word write
Parity/-Only word read/write access
System Registers
The system registers are only writeable by IU in the supervisor mode or by DMA during
halt mode.
Table 2.
System Registers Address Map
System Register Name
System Control Register
Software Reset
Power Down
System Fault Status Register
Failing Address Register
Error & Reset Status Register
Test Control Register
SYSCTR
SWRST
PDOWN
SYSFSR
FAILAR
ERRRSR
TESCTR
Address
0x 01F8 0000
0x 01F8 0004
0x 01F8 0008
0x 01F8 00A0
0x 01F8 00A4
0x 01F8 00B0
0x 01F8 00D0
6
TSC695FL
4204C–AERO–05/05
ATMEL [ ATMEL CORPORATION ]
