TSC695FL
Test and Diagnostic
Hardware Functions
A variety of TSC695FL test and diagnostic hardware functions, including boundary
scan, internal scan, clock control and On-chip Debugger, are controlled through an
IEEE 1149.1 (JTAG) standard Test Access Port (TAP).
Test Access Port
The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695FL chip. These
pins are:
–
–
–
–
–
TCK (input): Test Clock
TMS (input): Test Mode Select
TDI (input): Test Data Input
TDO (output): Test Data Output
TRST (input): Test Reset
Instruction Register
Five standard instructions are supported by the TSC695FL TAP.
Binary Value Name of Instruction Data Register
Scan Chain Accessed
Boundary Scan
00. 0000
00. 0001
EXTEST
Register
Boundary scan chain
Boundary scan chain
Boundary Scan
Register
SAMPLE/PRELOAD
Boundary Scan
Register
00. 0011
11. 1111
10. 0000
INTEST
BYPASS
IDCODE
Boundary scan chain
Bypass register
Bypass Register
Device ID Register
ID register scan chain
Debugging
The design is highly testable with the support of an On-Chip Debugger (OCD), an inter-
nal and boundary scan through JTAG interface.
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4204C–AERO–05/05
ATMEL [ ATMEL ]
