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5962-0324601QXC 参数 Datasheet PDF下载

5962-0324601QXC图片预览
型号: 5962-0324601QXC
PDF下载: 下载PDF文件 查看货源
内容描述: 低压抗辐射的32位SPARC嵌入式处理器 [Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器异步传输模式ATM时钟
文件页数/大小: 42 页 / 3365 K
品牌: ATMEL [ ATMEL ]
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This RESET output has a minimum of 1024 SYSCLK width to allow the usage of flash  
memories.  
The error and Reset Status Register contain the source of the last processor reset.  
Run Mode  
In this mode the IU/FPU is executing, while all peripherals are running (if software  
enabled).  
System Halt Mode  
System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU  
and FPU are frozen, while the timers (includeing the internal watchdog timer) and  
UART’s are stopped.  
Power Down Mode  
Error Halt Mode  
This mode is entered by writing to the Power Down Register. In this mode, the IU and  
FPU are frozen. The TSC695FL leaves the power-down mode if an external interrupt is  
asserted.  
Error Halt mode is entered under the following circumstances:  
A internal hardware parity error.  
The IU enters error mode.  
The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET.  
Error Handler  
The TSC695FL has one error output signal (SYSERR) which indicates that an  
unmasked error has occurred. Any error signalled on the error inputs from the IU and  
the FPU is latched and reflected in the Error and Reset Status Register. By default, an  
error leads to a processor halt.  
Parity Checking  
The TSC695FL includes:  
Parity checking and generation (if required) on the external data bus,  
Parity checking on the external address bus,  
Parity checking on ASI and SIZE,  
Parity checking and generation on all system registers,  
Parity generation and checking on the internal control bus to the IU,  
All external parity checking can be disabled using the NOPAR signal.  
System Clock  
The TSC695FL uses CLK2 clock input directly and creates a system clock signal by  
dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli-  
cation. It is highly recommended that only SYSCLK rising edge is used as reference as  
far as possible.  
System Availability  
Test Mode  
The SYSAV bit in the Error and Reset Status Register can be used by software to indi-  
cate system availability.  
The TSC695FL includes a number of software test facilities such as EDAC test, Parity  
test, Interrupt test, Error test and a simple Test Access Port. These test functions are  
controlled using the Test Control Register.  
12  
TSC695FL  
4204C–AERO–05/05