Interfaces
The TSS901E consists of the following blocks (See Figure 1):
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bidirectional link channels,
all comprising the DS-link macro cell (DSM), receive
and transmit sections (each including FIFOs) and a protocol processing unit (PPU).
Each channel allows full duplex communication up to 200 Mbit/s in each direction.
With protocol command execution a higher level of communication is supported.
Link disconnect detection and parity check at token level are performed. A
checksum generation for a check at packet level can be enabled.
The transmit rate is selectable between 1.25 and 200 Mbit/s; an additional power
saving mode can be enabled, where the transmit rate is automatically reduced to 10
Mbit/s when only Null tokens are being transmitted over the link. The default trans-
mit rate is 10 Mbit/s. For special applications the data transmit rate can be
programmed to values even below 10 Mbit/s; the lowest possible (to be within the
IEEE-1355 specification) transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5
Mbit/s).
•
Communication Memory Interface (COMI)
performs autonomous accesses to the
communication memory of the module to store data received via the links or to read
data to be transmitted via the links. The COMI consists of individual memory
address generators for the receive and transmit direction of every DS link channel.
The access to the memory is controlled via an arbitration unit providing a fair
arbitration scheme. Two TSS901E can share one DPRAM without external
arbitration.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any
CPU type.
Operation in little or big endian mode is configurable through internal registers.
The COMI address bus is 16 bit wide allowing direct access of up to 64K words of
the DPRAM. Two chip select signals are provided to allow splitting of the 64k
address space in two memory banks.
•
Host Control Interface (HOCI)
gives read and write access to the TSS901E
configuration registers and to the DS-link channels for the controlling CPU. Viewed
from the CPU, the interface behaves like a peripheral that generates acknowledges
to synchronize the data transfers and which is located somewhere in the CPU's
address space.
Packets can be transmitted or received directly via the HOCI. In this case the Com-
munication Memory (DPRAM) is not strictly needed. However, in this case the
packet size should be limited to avoid frequent CPU interaction.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any
CPU type. The byte alignment can be configured for little or big endian mode
through an external pin.
Additionally the HOCI contains the interrupt signalling capability of the TSS901E by
providing an interrupt output, the interrupt status register and interrupt mask register
to the local CPU.
A special pin is provided to select between control of the TSS901E by HOCI or by
link. If control by link is enabled, the host data bus functions as a 32-bit general pur-
pose interface (GPIO).
•
•
Protocol Command Interface (PRCI)
that collects the decoded commands from all
PPUs and forwards them to external circuitry via 5 special pins.
JTAG Test Interface
that represents the boundary scan testing provisions specified
by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSS901E'
test access port and on-chip circuitry is fully compliant with the IEEE 1149.1
specification. The test access port enables boundary scan testing of circuitry
connected to the TSS901E I/O pins.
3
TSS901E
Rev. C – 24-Aug-01
ATMEL [ ATMEL CORPORATION ]
