TSS901E
Introduction
The TSS901E provides an interface between a Data-Strobe link according to the IEEE
Std 1355-1995 specification carrying the simple interprocessor communication proto-
col
(1)
and a data processing node consisting of a CPU and communication and data
memory. The TSS901E provides HW supported execution of the major parts of the sim-
ple interprocessor communication protocol, particularly:
•
•
•
transfer of data between two modes of a multi-processor system with minimal host
CPU intervention,
execution of simple commands to provide basic features for system control
functions,
provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of
the transmit rate (TSS901E automatically reduces transmit rate for sending null tokens)
also low power usage is supported.
Figure 1.
TSS901E Block Diagram
Receive
COMI
RX1_DS
TX1_DS
DS
macro
cell
CADR
CCTRL
CDATA
Protocol
HADR
HCTRL
Transmit
HOCI
Channel 1
HINT
HDATA
RX2_DS
TX2_DS
Channel 2
PRCI
RCPU
SES
UTIL
RX3_DS
TX3_DS
Channel 3
Test
JTAG
Target applications are heterogeneous multi-processor systems supported by scalable
interfaces including the little/big endian swapping. The TSS901E connects modules with
different processors (e.g. TSC21020F, ERC32, TSC695E and others). Any kind of net-
work topology could be realized through the high speed point-to-point IEEE1355-links
(see chapter Applications).
1.
Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIP-
SAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users
guide.
2
Rev. C – 24-Aug-01
ATMEL [ ATMEL CORPORATION ]
