1 (ROM fetch)
2 (8-bit ROM fetch or load word)
byte 1 byte 2
(n-1) ws (n-1) ws
3 (ROM fetch)
byte 0
(n-1) ws
byte 3
(n-1) ws
start of
cycle
end of
cycle
t2
SYSCLK
ALE*
t14
t4
t4_1
t4_1
t4_1
RSIZE[0,1]
RA[31-0]
BA[0,1]
10
t4_1
FA2
FA1
FA2
t23
(address mod. 4)
t23
t23
t23
0
1
2
3
0
t5
t5
t5
ROMCS*
MEMCS*[0]
DDIR
MEMWR*
t15
t57
t56
t15
BUFFEN*
t8
t8
OE*
data driven by external buffers (c.f BUFFEN*)
D[31-8]
t10
t10
t10
FD2-2
t10
t9
t9
t9
t9
D[7-0]
INST
FD2-0
FD2-1
FD2-3
t60
t60
t16
(1 = fetch,
0 = load word)
t16
t16
MHOLD*
MDS*
t17
t17
t17