Figure 9. External Data Memory Read Cycle
TWHLH
ALE
PSEN
WR
TLLWL
TWLWH
TQVWX
TWHQX
TLLAX
A0-A7
TQVWH
DATA OUT
PORT 0
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8-A15 OR SFR P2
Table 6. Serial Port Timing – Shift Register Mode (ns)
30 MHz
Symbol
TXLXL
Parameter
Min Max
Serial port clock cycle time
400
300
50
TQVHX
TXHQX
TXHDX
TXHDV
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
0
300
Figure 10. Shift Register Timing Waveforms
0
1
2
3
4
5
6
7
8
INSTRUCTION
ALE
TXLXL
CLOCK
TXHQX
1
TQVXH
0
2
3
4
5
6
7
OUTPUT DATA
TXHDX
SET TI
VALID
SET RI
TXHDV
WRITE to SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
14
80C32E
4149N–AERO–04/07
ATMEL [ ATMEL ]
