TS8388B
Table 3.
Electrical Specifications (Continued)
Test
Level
4
4
Value
Min
100
40
Typ
125
50
Max
150
60
Unit
ppm/
°
C
ppm/
°
C
Note
Parameter
Gain error drift
Offset error drift
Symbol
–
–
DC Accuracy (CQFP68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70
°
C.
Differential non linearity
Differential non linearity
Integral non linearity
Integral non linearity
No missing code
Gain error
Input offset voltage
Gain error drift
Offset error drift
Transient Performance
Bit Error Rate
F
S
= 1 GSPS F
IN
= 62.5 MHz
ADC settling time
V
IN
-V
INB
= 400 mVpp
Overvoltage recovery time
BER
TS
TOR
4
4
4
–
–
–
–
0.5
0.5
1E-12
1
1
Error/
sample
ns
ns
DNL-
DNL+
INL-
INL+
–
–
–
–
–
1, 2
6
1, 2
6
1, 2
6
1, 2
6
-0.5
-0.6
–
–
-1.0
-1.2
–
–
-0.25
-0.35
0.3
0.4
0.7
0.9
0.7
0.9
–
–
0.6
0.7
–
–
1.0
1.2
lsb
lsb
lsb
lsb
lsb
lsb
lsb
lsb
Guaranteed over specified temperature range
1, 2
6
1, 2
6
4
4
-10
-11
-26
-30
100
40
-2
-2
-5
-5
125
50
10
11
26
30
150
60
% F
S
% F
S
mV
mV
ppm/
°
C
ppm/
°
C
AC Performance
Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj = 70
°
C, unless otherwise specified.
Signal to Noise and Distortion ratio
F
S
= 1 GSPS, F
IN
= 20 MHz
F
S
= 1 GSPS, F
IN
= 500 MHz
F
S
= 1 GSPS, F
IN
= 1000 MHz (-1 dBFs)
F
S
= 50 MSPS, F
IN
= 25 MHz
SINAD
–
4
4
4
1, 2, 6
–
42
41
38
40
–
44
43
40
44
–
–
–
–
–
–
dB
dB
dB
dB
7
2144C–BDC–04/03
ATMEL [ ATMEL CORPORATION ]
