Table 3.
Electrical Specifications (Continued)
Test
Level
Value
Min
Typ
Max
Unit
Note
Parameter
Symbol
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj (typical) = 70
°
C.
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD
)
(See Application Notes)
Differential output voltage swings
(assuming V
PLUSD
= 0V):
75Ω open transmission lines (ECL levels)
75Ω differentially terminated
50Ω differentially terminated
Output levels (assuming V
PLUSD
= 0V)
75Ω open transmission lines:
Logic “0” voltage
Logic “1” voltage
Output levels (assuming V
PLUSD
= 0V)
75Ω differentially terminated:
Logic “0” voltage
Logic “1” voltage
Output levels (assuming V
PLUSD
= 0V)
50Ω differentially terminated:
Logic “0” voltage
Logic “1” voltage
Differential Output Swing
Output level drift with temperature
–
–
ECL or LVDS
–
–
–
–
–
–
V
OL
V
OH
–
V
OL
V
OH
–
V
OL
V
OH
DOS
–
4
–
–
–
4
–
–
4
–
–
–
1, 2
6
1, 2
6
4
4
–
1.5
0.70
0.54
–
–
-0.88
–
–
-1.07
–
–
–
-1.16
-1.25
270
–
–
1.620
0.825
0.660
–
-1.62
-0.8
–
-1.41
-1
–
-1.40
-1.40
-1.10
-1.10
300
–
–
–
–
–
–
-1.54
–
–
-1.34
–
–
-1.32
-1.25
–
–
–
1.6
–
V
V
V
–
V
V
–
V
V
–
V
V
V
V
mV
mV/
°
C
DC Accuracy (CBGA68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
Tj (typical) = 70
°
C.
Differential non linearity
Differential non linearity
Integral non linearity
Integral non linearity
No missing codes
Gain
Input offset voltage
DNL-
DNL+
INL-
INL+
–
–
–
1
1
1
1
-0.6
–
-1.2
–
-0.4
0.4
-0.7
0.7
–
0.6
–
1.2
lsb
lsb
lsb
lsb
Guaranteed over specified temperature range
1, 2
1, 2
90
-26
98
-5
110
26
%
mV
6
TS8388B
2144C–BDC–04/03
ATMEL [ ATMEL CORPORATION ]
