AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.2 Internal ROM Default Settings
AX88179 supports internal ROM default settings inside chip hardware to enable it to communicate with USB host
controller during enumeration when the AX88179 EEPROM is blank (prior to being programmed) or the value of
EEPROM Checksum field is wrong or the 1st byte data of EEPROM is 0xFF. The default settings inside chip facilitate
users to update the EEPROM content through a Windows PC during R&D validation process or program a blank
EEPROM/eFuse during manufacturing process.
Below table shows AX88179’s internal ROM default settings being used in the case of blank EEPROM or
EEPROM with wrong checksum value or 1st byte data is 0xFF on board. Each of the address offset contains 16-bit data
from left to right representing the low-byte and high-byte, respectively. For example, in offset address 0x01, the ‘C6’ is
low-byte data and the ‘81’ is high-byte data.
Offset
Address
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0
8
1
9
2
A
3
B
4
C
5
D
6
E
7
F
00 E0
41 58
00 00
63 2E
30 30
16 00
01 0A
40 00
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
00 0E
80 0B
31 37
00 00
6F 72
30 30
10 02
00 00
0D 49
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
C6 81
09 04
39 00
00 00
70 2E
30 30
02 00
00 00
90 41
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
79 01
0E 07
00 00
41 53
00 00
30 30
00 00
00 00
00 40
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
90 17
1A 10
00 00
49 58
00 00
30 30
0A 10
00 00
00 80
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
95 0B
26 0E
00 00
20 45
00 00
30 31
03 00
F3 FF
20 08
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
B7 73
2D 16
00 00
6C 65
00 00
05 0F
0E 00
40 42
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
3E 01
38 38
00 00
20 43
30 30
02 07
FF 07
40 30
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
0x78
0x80~FF
Note: The 6 bytes from Internal ROM memory offset 42h to offset 44h are unused.
Table 7 : Internal ROM Memory Map
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