AX88178
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
I3
I5
O2
O3
O5
B
Input, 2.5V with 3.3V tolerant
Input, 3.3V
Input, 3.3V with 5V tolerant
Output, 2.5V with 3.3V tolerant
Output, 3.3V
B2
B5
PU
PD
P
Bi-directional I/O, 2.5V with 3.3V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
Internal Pull Up (75K)
Internal Pull Down (75K)
Power Pin
Output, 3.3V with 5V tolerant
Bi-directional I/O
S
Schmitt Trigger
Table 1: Pinout Description
Pin Name
Type
Pin No
Pin Description
USB Interface
DP
DM
DPRS
B
B
B
32
31
36
USB 2.0 data positive pin.
USB 2.0 data negative pin.
USB 1.1 data positive pin. Please connect to DP through a 39ohm
(+/-1%) serial resistor.
DMRS
B
35
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
VBUS
XIN12M
I5/PD/S
I3
10
26
VBUS pin input. Please connect to USB bus power.
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate.
XOUT12M
RREF
O3
I
27
30
12Mhz crystal or oscillator clock output.
For USB PHY’s internal biasing. Please connect to AGND through a
12.1Kohm (+/-1%) resistor.
RPU
I
34
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Interface
MDC
O2
121
120
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
MDIO
B2/PU
MDINT
I2/PU
I2
117
104
Station Management Interrupt input.
MII/GMII/RGMII Interface
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII/GMII/RGMII interface.
RX_CLK
RXD [7:0]
I2
114, 113, Receive Data. RXD [7:0] is driven synchronously with respect to
112, 111, RX_CLK by PHY. In RGMII mode, only RXD [3:0] is used.
110, 109,
108, 107
RX_DV
RX_ER
I2
I2
105
106
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [7:0]. In RGMII mode, RX_DV acts as RX_CTL.
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
Collision Detected. COL is driven high by PHY when the collision is
detected.
COL
CRS
I2
I2
116
115
Carrier Sense. CRS is asserted high asynchronously by the PHY when
either transmit or receive medium is non-idle.
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