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AX88178 参数 Datasheet PDF下载

AX88178图片预览
型号: AX88178
PDF下载: 下载PDF文件 查看货源
内容描述: USB转10/100/1000千兆位以太网/ HomePNA的控制器 [USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 37 页 / 930 K
品牌: ASIX [ ASIX ELECTRONICS CORPORATION ]
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AX88178  
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller  
6.2.2 Remote Wakeup Description  
After AX88178 enters into suspend mode, either the USB host or AX88178 itself can awake it up and resume back to the  
original operation mode before it entered suspend. Following truth table shows the chip setting, wakeup event, and device  
response supported by this ASIC. Note that “X” stands for don’t-care.  
Wakeup  
by  
Setting  
Wakeup Event  
Device  
awakes up?  
RWU bit Set_Feature RWLU of RWMP of Host send Receiving EXTWAKE Linkup  
Linkup  
of Flag  
byte in  
EEPRO  
M
X
0
1
1
standard  
command  
Monitor  
Mode  
Register  
Monitor  
Mode  
register  
resume  
signal  
Magic  
Packet  
UP_N pin detected detected on  
on  
Primary  
Phy  
Secondary  
Phy  
Host  
X
0
1
1
1
1
X
X
0
1
1
X
X
1
0
0
J -> K  
Yes  
No  
Yes  
Yes  
Yes  
Yes  
Device  
Device  
Device  
Device  
Device  
X
Yes  
X
X
X
Yes  
1
1
Yes  
X
X
Low-pulse  
Table 5: Remote Wakeup Truth Table  
6.3 Interrupt Endpoint  
The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A100_BB00_CCDD_EEFF.  
Where BB byte in byte 3:  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
MDINT  
Bit2  
FLE  
Bit1  
SPLS  
Bit0  
PPLS  
Reserved  
PPLS: Primarily PHY Link State.  
1: Link is up.  
0: Link is down.  
SPLS: Secondary PHY Link State.  
1: Link is up.  
0: Link is down.  
FLE: Bulk Out Ethernet Frame Length Error.  
1: Proprietary Length field has parity error during Bulk Out transaction.  
0: Proprietary Length field has no parity error during Bulk Out transaction.  
MDINT: Input level of MDINT pin. The MDINT pin can be connected to MDINT# pin of Ethernet Phy.  
1: When MDINT input pin = 1.  
0: When MDINT input pin = 0.  
CCDD byte in byte 5 and 6: Primary Phy’s register value, whose offset is given in High byte of EEPROM offset 0Fh.  
EEFF byte in byte 7 and 8: Primary Phy’s register value, whose offset is given in Low byte of EEPROM offset 0Fh.  
25  
ASIX ELECTRONICS CORPORATION  
 
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