欢迎访问ic37.com |
会员登录 免费注册
发布采购

AX88178 参数 Datasheet PDF下载

AX88178图片预览
型号: AX88178
PDF下载: 下载PDF文件 查看货源
内容描述: USB转10/100/1000千兆位以太网/ HomePNA的控制器 [USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 37 页 / 930 K
品牌: ASIX [ ASIX ELECTRONICS CORPORATION ]
 浏览型号AX88178的Datasheet PDF文件第20页浏览型号AX88178的Datasheet PDF文件第21页浏览型号AX88178的Datasheet PDF文件第22页浏览型号AX88178的Datasheet PDF文件第23页浏览型号AX88178的Datasheet PDF文件第25页浏览型号AX88178的Datasheet PDF文件第26页浏览型号AX88178的Datasheet PDF文件第27页浏览型号AX88178的Datasheet PDF文件第28页  
AX88178  
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller  
6.2.1.22 GPIO Register (1Fh, write only)  
Bit7  
RSE  
Bit6  
Reserved  
Bit5  
GPO_2  
Bit4  
GPO2EN  
Bit3  
Bit2  
Bit1  
Bit0  
GPO0EN  
GPO_1 GPO1EN GPO_0  
GPO0EN: Pin GPIO0 Output Enable.  
1: Output is enabled (meaning GPIO0 is used as an output pin).  
0: Output is tri-stated (meaning GPIO0 is used as an input pin) (default).  
GPO_0: Pin GPIO0 Output Value.  
GPO1EN: Pin GPIO1 Output Enable.  
1: Output is enabled (meaning GPIO1 is used as an output pin).  
0: Output is tri-stated (meaning GPIO1 is used as an input pin) (default).  
GPO_1: Pin GPIO1 Output Value.  
0: (default).  
GPO2EN: Pin GPIO2 Output Enable.  
1: Output is enabled (meaning GPIO2 is used as an output pin).  
0: Output is tri-stated (meaning GPIO2 is used as an input pin) (default).  
GPO_2: Pin GPIO2 Output Value.  
0: (default).  
RSE: Reload Serial EEPROM.  
1: Enable.  
0: Disabled (default)  
6.2.1.23 Software Reset Register (20h, write only)  
Bit7  
0
Bit6  
1
Bit5  
0
Bit4  
BZ  
Bit3  
PRL  
Bit2  
PRTE  
Bit1  
RT  
Bit0  
RR  
RR: Clear frame length error for Bulk In.  
1: set high to clear state.  
0: set low to exit clear state (default).  
RT: Clear frame length error for Bulk Out.  
1: set high to enter clear state.  
0: set low to exit clear state (default).  
PRTE: External Phy Reset pin Tri-state Enable.  
1: Enable, i.e., the external PHYRST_N pin is tri-stated (default). This allows the PHYRST_N pin’s active level to  
be controlled by external pulled-up (active high during power-on) or pulled-down resistor (active low during  
power-on).  
0: Disabled, i.e., the external PHYRST_N pin’s level is driven by either PRL bit or internal “USB RESET” based on  
the setting in SCPR bit in Flag byte of EEPROM.  
PRL: External Phy Reset pin Level. When SCPR bit = 1 and PRTE = 0, this bit controls the output level of external  
PHYRST_N pin.  
1: Set to high (default).  
0: Set to low.  
BZ: Force Bulk In to return a Zero-length packet.  
1: Software can force Bulk In to return a zero-length USB packet.  
0: Normal operation mode (default).  
Bit [7:5]: Please always write 010 to these bits.  
24  
ASIX ELECTRONICS CORPORATION  
 复制成功!