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DS760SL-3-001 参数 Datasheet PDF下载

DS760SL-3-001图片预览
型号: DS760SL-3-001
PDF下载: 下载PDF文件 查看货源
内容描述: [760 Watts Bulk Front End]
分类和应用:
文件页数/大小: 7 页 / 1367 K
品牌: ARTESYN [ ARTESYN TECHNOLOGIES ]
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DS760SL Series Data Sheet  
Outputs - All Models  
Turn On/Off Timing  
Item  
Description  
Min  
10  
1
Max  
300  
Units  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
mSec  
Tvout_rise  
+12 Output rise time  
Tvout_rise  
5.0 Vsb output rise time  
50  
Tsb_on_delay  
Tac_on_delay  
Tvout_holdup  
Tpwok_holdup  
Tpson_on_delay  
Tpson_pwok  
Tacok_delay  
Tpwok_on  
Delay from AC being applied to 5.0 Vsb being within regulation.  
Delay from AC being applied to all output voltages being within regulation.  
Time all output voltages, including 5.0 Vsb, stay within regulation after loss of AC.  
Delay from loss of AC to de-assertion of PWOK  
1500  
3000  
12  
5
Delay from PSON# active to output voltages within regulation limits.  
Delay from PSON# de-active to PWOK being de-asserted.  
Delay from loss of AC input to de-assertion of ACOK#.  
50  
2500  
100  
10  
100  
1
Delay from output voltages within regulation limits to PWOK asserted at turn on.  
Delay from PWOK de-asserted to 12 Vdc or 5.0 Vsb dropping out of regulation limits.  
Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON# signal.  
Delay from 5.0 Vsb being in regulation to 12 Vdc being in regulation at AC turn on.  
1000  
1000  
Tpwok_off  
Tpwok_low  
Tsb_vout  
100  
50  
1000  
PSON #  
PWOK# (POWER GOOD)  
The PSON# signal is required to remotely turn on/off the power  
supply. PSON# is an active low signal that turns on the +12 Vdc  
power rail. When this signal is not pulled low by the system, or left  
open, the +12 Vdc output turns off. The 5.0 Vsb output remains  
on. This signal is pulled to a standby voltage by a pull-up resistor  
internal to the power supply. The power supply fan(s) shall operate  
at the lowest speed.  
PPWOK is a power good signal and will assert HIGH when the  
outputs are within the regulation limits. PWOK will be pulled LOW  
by the power supply to indicate when either output falls below  
regulation limits or when AC power has been removed for a time  
sufficiently long so that power supply operation is no longer guaran-  
teed. The start of the PWOK# delay time shall be inhibited as long  
as the +12 Vdc output is in current limit or the 5.0 Vsb output is  
below the regulation limit.  
PSON Signal Characteristics  
PWOK Signal Characteristics  
Signal Type  
Accepts an open collector/drain  
input from the system. Pulled-up  
to the 5.0 Vsb located in power  
supply.  
Signal Type  
Open collector/drain output  
from power supply. Pullup to  
5.0 Vsb external to the power  
supply.  
PWOK = High  
PWOK = Low  
Power Good  
PSON# = Low  
PSON# = Open  
ON  
Power Not Good  
OFF  
MIN  
0 V  
MAX  
0.8 V  
MIN  
0 V  
MAX  
0.8 V  
To tLogic level low voltage, Ising = 4 mA  
Logic level high voltage, Isource = 200 µA  
Sink current, PWOK = low  
Logic level low (power supply ON)  
Logic level high (power supply OFF)  
Source current, Vpson = low  
2.0 V  
4.125 V  
4 mA  
2.0 V  
4.125 V  
4 mA  
Source current, PWOK = high  
2 mA  
Power up delay: Tpson_on_delay  
5 msec  
200 msec  
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