CS1630/31
6.41 Configuration 60 (Config60) – Address 92
7
6
5
4
3
2
1
0
-
PLC
-
CS_DELAY2 CS_DELAY1 CS_DELAY0
-
-
Number
Name
Description
[7]
[6]
[5]
-
PLC
-
Reserved
Configures the power line calibration (PLC) mode.
0 = Enable
1 = Disable
Reserved
Configures the I
comparator delay and board delays incurred through
Sense
FET switching T1
steps of 50ns.
. Switching time T1
can be set from 0ns to 350ns in
comp
comp
[4:2]
[1:0]
CS_DELAY[2:0]
-
T1comp = CS_DELAY[2:0] 50ns
Reserved
6.42 Configuration 61 (Config61) – Address 93
7
6
5
4
3
2
1
0
DITNODIM
DITLEVEL1
DITLEVEL0
DITCHAN
-
-
-
-
Number
Name
Description
Configures dithering, if enabled, to work in No-dimmer mode only.
0 = Dithering works in all modes
[7]
DITNODIM
1 = Dithering works in No-dimmer mode only
Configures the second stage dithering level based on the percentage of varia-
tion on the I DAC reference setting.
Sense
00 = 1.3%
01 = 2.9%
10 = 6%
[6:5]
DITLEVEL[1:0]
11 = 12.3%
Selects the channel for less dithering for which the nominal dither level, set
using bits DITLEVEL[1:0], is attenuated by the amount set by bits DITATT[1:0].
[4]
DITCHAN
-
0 = Channel 1
1 = Channel 2
[3:0]
Reserved
DS954F2
49
APEX [ CIRRUS LOGIC ]
