CS1630/31
6.12 Configuration 7 (Config7) – Address 39
7
6
5
4
3
2
1
0
PROBE
PRCNT3
PRCNT2
PRCNT1
PRCNT0
-
-
-
Number
Name
Description
probe operation that measures the resonant
Configures the automated T
RES
frequency on the drain of the second stage FET using the reflected voltage
applied to the FBAUX pin for improved valley switching performance.
[7]
PROBE
0 = Disables T
probe
RES
RES
1 = Enables T
probe
When PROBE=‘1’, sets the number of switching cycles TT
probe measurements.
between T
RES
Cycles
TTCycles = 16 PRCNT[3:0] + 15
[6:3]
[2:0]
PRCNT[3:0]
When PROBE=‘0’, sets the time for a quarter period of the resonant period
T
.
RES
TRES
-------------
4
= 2 PRCNT[3:0] 50ns
-
Reserved
6.13 Configuration 8 (Config8) – Address 40
7
6
5
4
3
2
1
0
RSHIFT3
RSHIFT2
RSHIFT1
RSHIFT0
CH1_ZCD2
CH1_ZCD1
CH1_ZCD0 CH1CURMSB
Number
Name
Description
Sets the number of right shifts performed on the second stage PID integrator
value to generate a 10-bit threshold value for the peak control comparator. For
peak rectify mode, the threshold is calculated by a right shift of the integrator
value. If RSHIFT[3:0] is set to 12, the 24-bit integrator is shifted right 12 times
and the remaining bits represent the threshold value provided to the peak con-
trol comparator.
[7:4]
RSHIFT[3:0]
Sets fixed time delay T
to account for the delay of the second
CH1ZCD(Delay)
stage zero-current detection (ZCD) comparator during channel 1 switching
cycles when the voltage applied to the FBAUX pin falls below the 250mV ZCD
comparator threshold. Configuring T
is essential for good quasi-
[3:1]
[0]
CH1_ZCD[2:0]
CH1CURMSB
CH1ZCD(Delay)
resonant (valley switching) performance. The value is an unsigned integer in
the range of 0value7. The delay is defined by:
TCH1ZCDDelay = CH1_ZCD[2:0] 50ns
Most significant bit for the CH1CUR register (see "Channel 1 Output Current
(CH1CUR) – Address 41" on page 35).
34
DS954F2
APEX [ CIRRUS LOGIC ]
