CS1630/31
6.9 Configuration 4 (Config4) – Address 36
7
6
5
4
3
2
1
0
T2CH1GAIN5 T2CH1GAIN4 T2CH1GAIN3 T2CH1GAIN2 T2CH1GAIN1 T2CH1GAIN0
SYNC
POL_ZCD
Number
Name
Description
for channel 1, which is required
Sets T2 compensation gain T2
CH1CompGain
when T2 measurement compensation is enabled for flyback designs. The
value is an unsigned integer in the range of 0T2CH1GAIN[5:0]<63. Com-
pensated T2 time T2
used in the second stage charge regulation
Compensated
loop is given by:
[7:2]
T2CH1GAIN[5:0]
T2Compensated = T2Measured – TZCDRisingEdge T2CH1CompGain
where,
T2
is a decimal number in the range of 0.0T2
T2CH1CompGain = T2CH1GAIN[5:0] 0.0625
<4.0:
CH1CompGain
CH1CompGain
Enables the digital synchronization signal that indicates which channel the
controller is signaling for each gate switching period on the IC’s SYNC pin.
The SYNC bit should be enabled for non-isolated second stage designs
where the synchronizer circuit is directly driven from the IC's SYNC pin.
0 = Disables SYNC onto pin
[1]
[0]
SYNC
1 = Enables SYNC onto pin
Sets polarity of zero-current detection comparator output. Recommended to
set bit POL_ZCD to active-low polarity.
0 = Active-low polarity
POL_ZCD
1 = Positive polarity
6.10 Second Stage Dim (S2DIM) – Address 37
7
6
5
4
3
2
1
0
27
26
25
24
23
22
21
20
S2DIM sets the minimum dim for second stage (flyback, buck, or tapped buck). The register value is an un-
signed integer in the range of 0value255. Enforced minimum dim percentage dim
following equation:
is determined by the
min
S2DIM[7:0] 16 + 15
-------------------------------------------------------
dimmin
=
100
4095
6.11 Maximum TT (TTMAX) – Address 38
7
6
5
4
3
2
1
0
27
26
25
24
23
22
21
20
TTMAX sets the maximum allowable target period for the second stage TT. The register value is an unsigned
integer in the range of 0value255. The maximum TT period is determined by:
TTMAX[7:0] 128 + 127 50ns
The maximum period for TT can be configured from 6.35s to 1.63835ms.
DS954F2
33
APEX [ CIRRUS LOGIC ]
