CS1630/31
Figure 20 illustrates the tapped buck stage configured for
series output mode.
5.8.3 Auxiliary Winding Configuration
The second-stage inductor auxiliary winding is used for zero-
current detection (ZCD) and overvoltage protection (OVP). The
auxiliary winding is sensed through the FBAUX pin of the IC.
LED1+
VBST
C12
R15
D10
LED 1-
C9
Z3
5.8.4 Control Parameters
D8
D9
VCC
_
Q
The second-stage control parameters are set to assure:
D11
Q5
D
GND
R12
R16
C10
• Line Regulation — The LED current remains constant
despite a ±10% AC line voltage variation.
LED 2+
C11
L3
LED 2-
CS1630/31
• Effect of Variation in Transformer Magnetizing
Inductance — The LED current remains constant over
a ±20% variation in magnetizing inductance.
IGND
Q4
13
15
GD
FBAUX
R13
R14
11
FBSENSE
The FBSENSE input is used to sense the current in the
second stage inductor. When this current reaches a certain
threshold, the gate drive turns ‘OFF’ (output on pin GD).
R11
GND
12
Two OTP values are required to set the second-stage output
currents, CH1CUR for channel 1 and CH2CUR for channel 2
(see "Channel 1 Output Current (CH1CUR) – Address 41" on
page 35 and "Channel 2 Output Current (CH2CUR) – Address
43" on page 35). Equations 6 and 7 are used to calculate the
values to be programmed into registers CH1CUR and
CH2CUR.
Figure 20. Tapped Buck Series Output Model
To maintain constant output current with minimum line-
frequency ripple, the following are required:
• For parallel configurations, a minimum voltage potential
difference between two strings
511 2 RSense ICH1
---------------------------------------------------------
CH1CUR =
CH2CUR =
[Eq.6]
[Eq.7]
N VSense
• For series configurations, a minimum current amplitude
difference between two strings
511 2 RSense ICH2
---------------------------------------------------------
N VSense
5.8.2 Primary-side Current Control for
Two-Channel Output
where,
RSense = Resistance of current sense resistor
Sense = Full scale voltage across sense resistor (~1.4V)
The CS1630/31 regulates two-channel output current
independently using primary-side control, which eliminates
the need for opto-coupler feedback. The control loop operates
in peak current control mode, with the peak current set cycle-
by-cycle by the two independent current regulation loops.
Demagnetization time of the second stage inductor is sensed
by the FBAUX pin using an auxiliary winding on the second
stage inductor. The FBAUX pin supplies an input to the digital
control loop.
V
I
I
CH1 = Target current in channel 1 LED string
CH2 = Target current in channel 2 LED string
RSense is determined by the input voltage, switching
frequency, auxiliary transformer turns ratio, target output
current and output voltage for each channel.
The zero-current detect input on pin FBAUX is used to
determine the demagnetization cycle T2. The controller then
uses these inputs to control the gate drive output, GD.
The power conversion for two-channel output is carried out by
interleaving the PWM. The two-channel control system
consists of two components:
5.8.5 Frequency Dithering
• A toggle device (phase synchronizer circuit) on the
secondary side that alternatively activates each output
channel for each switching event
The peak amplitude of switching harmonics can be reduced by
spreading the energy into wider spectrums. The frequency
dithering level can be managed using bits DITLEVEL[1:0] in
register Config61 (see "Configuration 61 (Config61) – Address
93" on page 49). Additionally, the CS1630/31 has an option to
enable dithering only in No-dimmer Mode by setting bit
DITNODIM to ‘1’. If output currents differ, the CS1630/31 also
has an option to allow for less dither on one of the two
channels by selecting the channel using bit DITCHAN. The
channel selected for less dither attenuates the dither level by
the percentage configured by bits DITATT[1:0].
• A digital sequencer on the primary side determines which
output channel is active for any given switching event
As the output is toggled between each channel, a sequencer
on the primary side identifies the current control phase and
regulates the current in each output channel. To ensure
proper operation for a parallel configuration, the two output
channels should target a voltage differential that is greater
than 20%. For a series configuration, the two output channels
should target a current differential that is greater than 20%.
18
DS954F2
APEX [ CIRRUS LOGIC ]
