AGD8156A / AGD8256A
Pin Configuration
VBU
HOU
VSU
NC
VCC
1
28
HINU
HINV
2
3
27
26
4
5
25
24
23
22
21
20
19
18
17
16
15
HINW
LINU
LINV
LINW
/FO
VBV
6
HOV
VSV
7
8
NC
9
ITRIP
EN
VBW
HOW
VSW
NC
10
11
12
13
14
RCIN
VSS
LOU
LOV
COM
LOW
SOP-28L
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
2
VCC
HINU
HINV
HINW
LINU
LINV
LINW
/FO
Low-Side Supply Voltage
High-Side Logic Input (U-Phase)
High-Side Logic Input (V-Phase)
3
4
High-Side Logic Input (W-Phase)
Low-Side Logic Input (U-Phase)
Low-Side Logic Input (V-Phase)
Low-Side Logic Input (W-Phase)
5
6
7
8
Fault Output with Open Drain (Indicates Over-Current and VCC UVLO)
Analog Input for Over-Current Shutdown
Enable I/O Functionality (Positive Logic)
External RC-Network Input used to define Fault Output Duration Time
Logic Ground
9
ITRIP
EN
10
11
12
13
14
15
16
17
18
19
RCIN
VSS
COM
LOW
LOV
Power Ground
Low-Side Driver Output (W-Phase)
Low-Side Driver Output (V-Phase)
LOU
NC
Low-Side Driver Output (U-Phase)
No Connection
VSW
High-Side Floating Supply Offset Voltage (W-Phase)
High-Side Driver Output (W-Phase)
HOW
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Page 3 of 14
Rev. 1.3 October 2018
AOS [ ALPHA & OMEGA SEMICONDUCTORS ]
