APW7061
Application Information (Cont.)
MOSFET Selection
· Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since thesenodes are fast moving signals. Therefore
keep traces to these nodes as short as possible.
The selection of the N-channel power MOSFETs are
determinedby the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.
The losses in the MOSFETs have two components:
conduction loss and transition loss. For the upper and
lower MOSFET, the losses are approximately given
by the following :
· The groundreturn of CIN must return to the combine
COUT (-) terminal.
· Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
2
VDS
PLOWER = Iout (1+ TC)(RDS(ON))(1-D)
2
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tswis the switching interval
D is the duty cycle
Note that bothMOSFETs have conduction losses while
theupper MOSFETinclude an additionaltransition loss.
The switching internal, tsw, is a function of the reverse
transfer capacitance CRSS. Figure 6 illustrates the
switching waveform internal of the MOSFET.
t
Time
sw
The (1+TC)term is to factorin thetemperaturedependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs
Temperature” curve of the power MOSFET.
Figure 6. Switching waveform across MOSFET
VIN
Layout Considerations
CIN
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be
minimized by using short, wide printed circuit traces.
Signal and power grounds are to be kept separate and
finally combined using ground plane construction or
single point grounding. Figure 8 illustrates the layout,
with bold lines indicat ing high current paths.
Components along the bold lines should be placed
close together. Below is a checklist for your layout:
APW7061
+
11
PGND
12
LGATE
L
O
A
D
COUT
U
1
9
Q1
UGATE
PHASE
Q2
+
8
L1
VOUT
Figure 7. Recommended Layout Diagram
Copyright ã ANPECElectronicsCorp.
13
www.anpec.com.tw
Rev. A.7 - Nov., 2005
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
