APW7061
Application Information (Cont.)
Compensation (Cont.)
The closed loop gain of the converter can be written
VIN
as:
R2
x GAINAMP
GAINLC x GAINPWM x
Driver
R1+R2
PWM
Comparator
Figure 5 shows the converter gain and the following
guidelines will help to design the compensation
network.
VOSC
Output of
Error
Amplifier
PHASE
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Use the following equation to calculate R3:
Driver
DVOSC
FESR
R1+ R2 FO
R3 =
´
´
´
Figure 3. The PWM Modulator
2
VIN
R2
gm
FLC
Where:
The compensation circuit is shown in Figure 4. R3
and C1 introduce a zero and C2 introduces a pole to
reduce the switching noise. The transfer function of
error amplifier is given by:
gm = 900uA/V
2.Place the zero FZ before the LC filter double poles
FLC:
é
1
1 ù
æ
ö
FZ = 0.75 x FLC
gm ´ çR3 +
÷//
GAINAMP = gm´ Zo =
ê
ú
sC1
sC2
Calculate the C1 by the equation:
è
ø
ë
û
1
1
æ
ö
÷
C1=
s +
ç
2´ p ´ R1´ 0.75´ FLC
3. Set the pole at the half the switching frequency:
FP = 0.5 x FS
R3 ´ C1
è
ø
= gm ´
C1+ C2
R3 ´ C1´ C2
æ
ö
s´ s +
´ C2
÷
ç
è
ø
Calculate the C2 by the equation:
The poles and zero of thecompensation network are:
1
C1
FP =
C2 =
C1´ C2
p ´ R3 ´ C1 ´ FS - 1
2´ p ´ R3´
C1+ C2
1
FZ
=
FZ=0.75FLC
2´ p ´ R3´ C1
F
P=0.5F
S
V
OUT
20 ×log(gm×R3)
Error
Compensation Gain
R1
Amplifier
Gain
FB
-
COMP
F
LC
F
O
VIN
20 ×log
R2
? VOSC
+
R3
C1
Converter
Gain
F
ESR
VREF
PWM &
Filter Gain
C2
Frequency
Figure 5. Converter Gain & Frequency
Figure 4. Compensation Network
Copyright ã ANPECElectronicsCorp.
12
www.anpec.com.tw
Rev. A.7 - Nov., 2005
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
