APW1172
Application Description (Cont.)
L
V O U T
Frequency Compensation (Cont.)
cause the phase decrease rapidly at the natural
frequency and lead the phase margin not enough to
maintain the stable status. The stable issue improved
by apply a zero in the frequency domain to increase
the phase margin.
ESR
Loading
CO U T
Ceram ic
type
FB PIN
Consider the Figure-2, find the transfer function H (s)
COMP PIN
EA
as:
SCOUT (ESR) +1
H(s) =
1.235V
RC1
CC1
S2 LCOUT + SCOUT (ESR) +1
1
CC2
pole =
1,2
2p LCOUT
1
zero1 =
2p(ESR)COUT
Adding a resistor and a capacitor at the COMP pin is
the simplest way to generate a zero. The placement
of the components is the show of Figure-1. The
1
L
Q =
(ESR) COUT
The pole1 and pole2 are the conjugate roots of the
denominator andthezero1istheroot of thenumerator.
Find the Q factor from the quadratic function and the
description of Q factor as above.
frequency of the zero is
1
fzero
=
(10)
2pRC1CC1
The relation of the zero and the natural frequency is
The frequency response of the output stage show as
Figure-3.
fzero = 0.8× fnatural
(11)
Locate the zero before the natural frequency to
compensatethephase.Theanothercapacitor CC2 used
to bypass the noise. In general
0db
slope=-40db/
1
decade
(12)
CC2
=
CC1
10
In the other applications, use the ceramic capacitor
as the output capacitor is very popular. Because the
small dimensionof theceramiccapacitor savethePCB
(Printed Circuit Board) area, the low ESR (Equivalent
Series Resistance) of the ceramic one decrease the
power dissipation of the output capacitor. But the
serious drawbacks of the ceramic one is the stable
issue.
0d
phase
-90d
-135d
-180d
f
Pole1,2
Figure-3
Zero1
Copyright ã ANPEC Electronics Corp.
15
www.anpec.com.tw
Rev. A.4 - Aug., 2005
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
