AAT3215
150mA CMOS High Performance LDO
mine the total true power dissipation under the var-
ied load.
High Peak Output Current Applications
Some applications require the LDO regulator to
operate at continuous nominal level with short
duration, high-current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, first calculate the power dissi-
pation at the nominal continuous level, then factor
in the additional power dissipation due to the short
duration, high-current peaks.
PD(total) = PD(100mA) + PD(150mA)
PD(total) = 156.6mW + 21mW
PD(total) = 177.6mW
The maximum power dissipation for the AAT3215
operating at an ambient temperature of 85°C is
211mW. The device in this example will have a total
power dissipation of 177.6mW. This is well within
the thermal limits for safe operation of the device.
For example, a 2.5V system using a AAT3215IGV-
2.5-T1 operates at a continuous 100mA load cur-
rent level and has short 150mA current peaks. The
current peak occurs for 378µs out of a 4.61ms peri-
od. It will be assumed the input voltage is 4.2V.
Printed Circuit Board Layout
Recommendations
In order to obtain the maximum performance from
the AAT3215 LDO regulator, careful consideration
should be given to the printed circuit board (PCB)
layout. If grounding connections are not properly
made, power supply ripple rejection, low output self
noise, and transient response can be compromised.
First, the current duty cycle in percent must be cal-
culated:
% Peak Duty Cycle: X/100 = 378µs/4.61ms
% Peak Duty Cycle = 8.2%
The LDO regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 150mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined then multiplied
by the duty cycle to conclude the actual power dis-
sipation over time.
Figure 1 shows a common LDO regulator layout
scheme. The LDO regulator, external capacitors
(CIN, COUT, and CBYP), and the load circuit are all
connected to a common ground plane. This type of
layout will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high performance appli-
cations, this method is not recommended.
PD(MAX)
= (VIN - VOUT)IOUT + (VIN · IGND)
PD(100mA) = (4.2V - 2.5V)100mA + (4.2V · 150µA)
PD(100mA) = 170.6mW
The problem with the layout in Figure 1 is the
bypass capacitor and output capacitor share the
same ground path to the LDO regulator ground pin,
along with the high current return path from the
load back to the power supply. The bypass capac-
itor node is connected directly to the LDO regulator
internal reference, making this node very sensitive
to noise or ripple. The internal reference output is
fed into the error amplifier, thus any noise or ripple
from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This
effect can increase noise seen on the LDO regula-
tor output, as well as reduce the maximum possible
power supply ripple rejection. There is PCB trace
impedance between the bypass capacitor connec-
tion to ground and the LDO regulator ground con-
nection. When the high load current returns
through this path, a small ripple voltage is created,
feeding into the CBYP loop.
PD(91.8%D/C) = %DC · PD(100mA)
PD(91.8%D/C) = 0.918 · 170.6mW
PD(91.8%D/C) = 156.6mW
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 156.6mW. Now the
power dissipation for the remaining 8.2% of the
duty cycle at the 150mA load can be calculated:
PD(MAX)
= (VIN - VOUT)IOUT + (VIN · IGND)
PD(150mA) = (4.2V - 2.5V)150mA + (4.2V · 150mA)
PD(150mA) = 255.6mW
PD(8.2%D/C) = %DC · PD(150mA)
PD(8.2%D/C) = 0.082 · 255.6mW
PD(8.2%D/C) = 21mW
The power dissipation for 150mA load occurring for
8.2% of the duty cycle will be 21mW. Finally, the
two power dissipation levels can summed to deter-
3215.2006.05.1.6
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