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AAT2515IWP-AA-T1 参数 Datasheet PDF下载

AAT2515IWP-AA-T1图片预览
型号: AAT2515IWP-AA-T1
PDF下载: 下载PDF文件 查看货源
内容描述: 两个600mA快速瞬态高频降压转换器 [Dual 600mA Fast Transient High Frequency Buck Converter]
分类和应用: 转换器
文件页数/大小: 20 页 / 616 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
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PRODUCT DATASHEET  
AAT2515  
SystemPowerTM  
Dual 600mA FastTransient High Frequency Buck Converter  
The input capacitor RMS ripple current varies with the  
input and output voltage and will always be less than or  
equal to half of the total DC load current of both convert-  
ers combined.  
the power leads from the bench power supply, most  
applications do not exhibit this problem.  
In applications where the input power source lead induc-  
tance cannot be reduced to a level that does not affect  
converter performance, a high ESR tantalum or alumi-  
num electrolytic capacitor should be placed in parallel  
with the low ESR, ESL bypass ceramic capacitor. This  
dampens the high Q network and stabilizes the system.  
IO1(MAX) + IO2(MAX)  
IRMS(MAX)  
=
2
This equation also makes the worst-case assumption  
that both converters are operating at 50% duty cycle  
and are synchronized. Since the converters are not syn-  
chronized and are not both operating at 50% duty cycle,  
the actual RMS current will always be less than this.  
Losses associated with the input ceramic capacitor are  
typically minimal.  
Output Capacitor  
The output capacitor limits the output ripple and pro-  
vides holdup during large load transitions. A 10μF X5R  
or X7R ceramic capacitor typically provides sufficient  
bulk capacitance to stabilize the output during large load  
transitions and has the ESR and ESL characteristics nec-  
essary for low output ripple.  
VO  
VO  
·
1 -  
VIN  
VIN  
The term  
appears in both the input voltage  
ripple and input capacitor RMS current equations. It is  
a maximum when VO is twice VIN. This is why the input  
voltage ripple and the input capacitor RMS current ripple  
are a maximum at 50% duty cycle.  
The output voltage droop due to a load transient is  
dominated by the capacitance of the ceramic output  
capacitor. During a step increase in load current the  
ceramic output capacitor alone supplies the load current  
until the loop responds. As the loop responds, the induc-  
tor current increases to match the load current demand.  
This typically takes several switching cycles and can be  
estimated by:  
The input capacitor provides a low impedance loop for the  
edges of pulsed current drawn by the AAT2515. Low ESR/  
ESL X7R and X5R ceramic capacitors are ideal for this  
function. To minimize the stray inductance, the capacitor  
should be placed as closely as possible to the IC. This  
keeps the high frequency content of the input current  
localized, minimizing EMI and input voltage ripple.  
3 · ΔILOAD  
=
COUT  
VDROOP · FS  
The proper placement of the input capacitor (C3 and C8)  
can be seen in the evaluation board layout in Figure 2.  
Since decoupling must be as close to the input pins as  
possible, it is necessary to use two decoupling capaci-  
tors. C3 provides the bulk capacitance required for both  
converters, while C8 is a high frequency bypass capaci-  
tor for the second channel (see C3 and C8 placement in  
Figure 2).  
Once the average inductor current increases to the DC  
load level, the output voltage recovers. The above equa-  
tion establishes a limit on the minimum value for the  
output capacitor with respect to load transients.  
The internal voltage loop compensation also limits the  
minimum output capacitor value to 10μF. This is due to  
its effect on the loop crossover frequency (bandwidth),  
phase margin, and gain margin. Increased output capac-  
itance will reduce the crossover frequency with greater  
phase margin.  
A laboratory test set-up typically consists of two long  
wires running from the bench power supply to the eval-  
uation board input voltage pins. The inductance of these  
wires, along with the low ESR ceramic input capacitor,  
can create a high Q network that may affect converter  
performance.  
The maximum output capacitor RMS ripple current is  
given by:  
This problem often becomes apparent in the form of  
excessive ringing in the output voltage during load tran-  
sients. Errors in the loop phase and gain measurements  
can also result.  
1
V
OUT · (VIN(MAX) - VOUT  
)
IRMS(MAX)  
=
·
L · F · VIN(MAX)  
2 · 3  
Dissipation due to the RMS current in the ceramic output  
capacitor ESR is typically minimal, resulting in less than  
a few degrees rise in hot spot temperature.  
Since the inductance of a short printed circuit board  
trace feeding the input voltage is significantly lower than  
w w w . a n a l o g i c t e c h . c o m  
2515.2007.12.1.0  
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