AAT2513
Dual 600mA Step-Down
Converter with Synchronization
This equation also makes the worst-case assump-
tion that both converters are operating at 50% duty
cycle synchronized.
should be placed in parallel with the low ESR, ESL
bypass ceramic. This dampens the high Q network
and stabilizes the system.
VO
⎛
⎝
VO
⎞
⎠
·
1 -
VIN
VIN
The term
appears in both the input
Output Capacitor
voltage ripple and input capacitor RMS current
equations. It is at maximum when VO is twice VIN.
This is why the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The output capacitor limits the output ripple and
provides holdup during large load transitions. A
4.7µF to 10µF X5R or X7R ceramic capacitor typi-
cally provides sufficient bulk capacitance to stabi-
lize the output during large load transitions and has
the ESR and ESL characteristics necessary for low
output ripple.
VO
VIN
⎛
· 1
⎝
VO
VIN
⎞
⎠
-
= D
(1 - D) = 0.52 = 0.25
⋅
The output voltage droop due to a load transient is
dominated by the capacitance of the ceramic out-
put capacitor. During a step increase in load cur-
rent the ceramic output capacitor alone supplies
the load current until the loop responds. As the loop
responds the inductor current increases to match
the load current demand. This typically takes two
to three switching cycles and can be estimated by:
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT2513. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
the stray inductance, the capacitor should be
placed as close as possible to the IC. This keeps
the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
3
·
VDROOP FS
ΔILOAD
COUT
=
The proper placement of the input capacitor (C3 and
C9) can be seen in the evaluation board layout in
Figures 3 and 4. Since decoupling must be as close
to the input pins as possible it is necessary to use
two decoupling capacitors, one for each converter.
·
Once the average inductor current increases to the
DC load level, the output voltage recovers. The
above equation establishes a limit on the minimum
value for the output capacitor with respect to load
transients.
A Laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires along with the low ESR ceram-
ic input capacitor can create a high Q network that
may effect the converter performance.
The internal voltage loop compensation also limits
the minimum output capacitor value to 4.7µF. This
is due to its effect on the loop crossover frequency
(bandwidth), phase margin, and gain margin.
Increased output capacitance will reduce the
crossover frequency with greater phase margin.
This problem often becomes apparent in the form
of excessive ringing in the output voltage during
load transients. Errors in the loop phase and gain
measurements can also result.
The maximum output capacitor RMS ripple current
is given by:
Since the inductance of a short printed circuit board
trace feeding the input voltage is significantly lower
than the power leads from the bench power supply,
most applications do not exhibit this problem.
1
V
OUT · (VIN(MAX) - VOUT
VIN(MAX)
)
IRMS(MAX)
=
·
L · F ·
2 · 3
In applications where the input power source lead
inductance cannot be reduced to a level that does
not effect the converter performance, a high ESR
tantalum or aluminum electrolytic (C10 of Figure 2)
Dissipation due to the RMS current in the ceramic
output capacitor ESR is typically minimal, resulting in
less than a few degrees rise in hot spot temperature.
2513.2007.04.1.1
13
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
