PRODUCT DATASHEET
AAT2146
TM
SwitchReg
Low Noise, FastTransient 600mA Step-Down Converter
for VIN = 2 · VO
Output Capacitor
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7μF to
10μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
IO
2
IRMS(MAX)
=
VO
VIN
⎛
VO
1 -
⎞
⎠
·
⎝
VIN
The term
appears in both the input voltage rip-
ple and input capacitor RMS current equations and is a
maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The output voltage droop due to a load transient is
dominated by the capacitance of the ceramic output
capacitor. During a step increase in load current, the
ceramic output capacitor alone supplies the load current
until the loop responds. Within two or three switching
cycles, the loop responds and the inductor current
increases to match the load current demand. The rela-
tionship of the output voltage droop during the three
switching cycles to the output capacitance can be esti-
mated by:
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT2146. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C2) can be
seen in the evaluation board layout in Figure 2.
3 · ΔILOAD
=
COUT
V
DROOP · FS
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients.
The internal voltage loop compensation also limits the
minimum output capacitor value to 4.7μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem.
The maximum output capacitor RMS ripple current is
given by:
In applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
1
VOUT · (VIN(MAX) - VOUT
)
IRMS(MAX)
=
·
L · F · VIN(MAX)
2 · 3
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
w w w . a n a l o g i c t e c h . c o m
12
2146.2008.10.1.2
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
