AAT1230/1230-1
18V 100mA Step-Up Converter
3. Minimize the distance between L1 to D1 and
switching pin SW; minimize the size of the PCB
area connected to the SW pin.
4. Maintain a ground plane and connect to the IC
RTN pin(s) as well as the GND terminals of C1
and C2.
5. Consider additional PCB area on D1 cathode
to maximize heatsinking capability. This may
be necessary when using a diode with a high
VF and/or thermal resistance.
6. When using the TDFN33-12 package, connect
paddle to SW pin or leave floating. Do not con-
nect to RTN/GND conductors.
PCB Layout Guidelines
Boost converter performance can be adversely
affected by poor layout. Possible impact includes
high input and output voltage ripple, poor EMI per-
formance, and reduced operating efficiency. Every
attempt should be made to optimize the layout in
order to minimize parasitic PCB effects (stray
resistance, capacitance, inductance) and EMI cou-
pling from the high frequency SW node.
A suggested PCB layout for the AAT1230/1230-1
boost converter is shown in Figures 3 and 4. The fol-
lowing PCB layout guidelines should be considered:
7. To avoid problems at startup, add a 10kΩ resis-
tor between the VIN, VP and EN/SET pins (R4).
This is critical in applications requiring immuni-
ty from input noise during “hot plug” events, e.g.
when plugged into an active USB port.
1. Minimize the distance from Capacitor C1 and
C2 negative terminal to the PGND pins. This
is especially true with output capacitor C2,
which conducts high ripple current from the
output diode back to the PGND pins.
2. Place the feedback resistors close to the output
terminals. Route the output pin directly to resis-
tor R1 to maintain good output regulation. R3
should be routed close to the output GND pin,
but should not share a significant return path
with output capacitor C2.
Figure 3: AAT1230/1230-1 Evaluation
Board Top Side.
Figure 4: AAT1230/1230-1 Evaluation
Board Bottom Side.
1230.2007.06.1.6
15
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