欢迎访问ic37.com |
会员登录 免费注册
发布采购

AAT1230IRN 参数 Datasheet PDF下载

AAT1230IRN图片预览
型号: AAT1230IRN
PDF下载: 下载PDF文件 查看货源
内容描述: 18V 100毫安升压转换器 [18V 100mA Step-Up Converter]
分类和应用: 转换器升压转换器
文件页数/大小: 21 页 / 454 K
品牌: ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
 浏览型号AAT1230IRN的Datasheet PDF文件第10页浏览型号AAT1230IRN的Datasheet PDF文件第11页浏览型号AAT1230IRN的Datasheet PDF文件第12页浏览型号AAT1230IRN的Datasheet PDF文件第13页浏览型号AAT1230IRN的Datasheet PDF文件第15页浏览型号AAT1230IRN的Datasheet PDF文件第16页浏览型号AAT1230IRN的Datasheet PDF文件第17页浏览型号AAT1230IRN的Datasheet PDF文件第18页  
AAT1230/1230-1  
18V 100mA Step-Up Converter  
Option 3: Dynamic Voltage Control Using  
abled, the register is reset to the default value, which  
sets the FB2 pin to 0.6V if EN is subsequently pulled  
high.  
2
S Cwire Interface  
The output can be dynamically adjusted by the host  
controller to any of 16 pre-set output voltage levels  
2
2
using the integrated S Cwire interface. The  
S Cwire Output Voltage Programming  
2
EN/SET pin serves as the S Cwire interface input.  
The AAT1230/1230-1 is programmed through the  
2
The SEL pin must be pulled low when using the  
S Cwire interface according to Table 2. The rising  
2
S Cwire interface.  
clock edges received through the EN/SET pin  
determine the feedback reference and output volt-  
age set-point. Upon power up with the SEL pin  
2
S Cwire Serial Interface  
2
low and prior to S Cwire programming, the default  
2
AnalogicTech's S Cwire serial interface is a propri-  
feedback reference voltage is set to 0.6V.  
etary high-speed single-wire interface available  
2
only from AnalogicTech. The S Cwire interface  
EN/SET  
Rising  
Edges  
FB2  
EN/SET  
FB2  
records rising edges of the EN/SET input and  
decodes into 16 different states. Each state corre-  
sponds to a voltage setting on the FB2 pin, as  
shown in Table 2.  
Reference  
Rising Reference  
Voltage (V)  
Edges Voltage (V)  
1
2
3
4
5
6
7
8
0.60 (Default)  
0.64  
9
0.92  
0.96  
1.00  
1.04  
1.08  
1.12  
1.16  
1.20  
10  
11  
12  
13  
14  
15  
16  
0.68  
0.72  
0.76  
0.80  
0.84  
0.88  
2
S Cwire Serial Interface Timing  
2
The S Cwire serial interface has flexible timing.  
Data can be clocked-in at speeds up to 1MHz. After  
data has been submitted, EN/SET is held high to  
latch the data for a period TLAT. The output is sub-  
sequently changed to the predetermined voltage.  
When EN/SET is set low for a time greater than  
TOFF, the AAT1230/1230-1 is disabled. When dis-  
2
Table 2: S Cwire Voltage Control Settings  
(SEL = Low).  
THI  
TOFF  
TLO  
TLAT  
EN/SET  
1
2
n-1  
n 16  
0
n-1  
Data Reg  
0
2
Figure 2: S Cwire Timing Diagram to Program the Output Voltage.  
14  
1230.2007.06.1.6  
 复制成功!