AAT1142
800mA Voltage-Scaling Step-Down Converter
LX
L1
2.2µH
U1
VIN
1
2
3
4
5
6
12
11
10
9
VOUT
VIN
LX
VIN
C4
(optional)
0.1µF
C2
10µF
PGND
AGND
C1
C3
4.7µF
(optional)
10µF
MODE/SYNC AGND
SDA
AGND
AGND
FB
1
2
R1
0
8
VIN
VIN
SCL
JP1
7
EN/SET
R5
1.8K
R4
1.8K
(optional)
R2
(optional)
AAT1142
TSOPJW-12
VIN
R3
10K
SDA
SCL
1
2
1
2
3
JP2
JP3
U1 AAT1142 TSOPJW-12
L1 CDRH2D14/2R2
C1 4.7µF 10V 0805 X5R
C2 10µF 10V 0805 X5R
C3 10µF optional
C4 0.1µF optional
R1 0Ω 0603
R2 optional 0603
R3 10K 0603
R4, R5 1.8K 0603
Figure 1: AAT1142 Evaluation Board Schematic.
put. To ensure a disable event, the EN/SET pulse
width must be greater than the latch time (500µs
maximum).
Applications Information
The AAT1142 output voltage may be programmed
from 0.6V to 2.0V through I2C or S2Cwire serial
interface. When using I2C or S2Cwire, the output
voltage can be programmed across the entire out-
put voltage range or in increments as small as
±50mV (see Figure 2).
The I2C serial interface requires a master to initiate
all the communications with slave devices. The I2C
protocol is a bidirectional bus allowing both read and
write actions to take place; while the AAT1142 is a
slave device and only supports the write protocol.
The AAT1142 is a receiver-only (or write-only)
slave device and the Read / Write (R/W) bit is set
low. The AAT1142 address is preset to 0x14 (Hex).
I2C Serial Interface
The AAT1142 is compatible with the I2C interface,
which is a widely used two-line serial interface.
The I2C two-wire communications bus consists of
SDA and SCL lines. SDA provides data, while SCL
provides clock input. SDA data consists of an
address bit sequence followed by a data bit
sequence. SDA data transfer is synchronized to
SCL rising clock edges.
I2C START and STOP Conditions
START and STOP conditions are initialized by the
I2C bus master. The master determines the START
(beginning) and STOP (end) of a transfer with the
slave device. Prior to initiating a START or after
STOP, both the SDA and SCL lines are in bus-free
mode. Bus-free mode is when SDA and SCL are
both in the high state (see Figure 3).
When using the I2C interface, EN/SET is pulled
high to enable the output or low to disable the out-
12
1142.2006.07.1.0
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
