PRODUCT DATASHEET
AAT1141
SwitchRegTM
FastTransient 600mA Step-Down Converter
a maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle.
The proper placement of the input capacitor (C2) can be
seen in the evaluation board layout in Figure 2.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT1141. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capacitor
should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
Figure 2: AAT1141 Sample Layout
Top Side.
Figure 3: Exploded View of Sample Layout.
Figure 4: AAT1141 Sample Layout
Bottom Side.
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