ARA2004
Table 1: Pin Description
PIN
1
NAME
GND
DESCRIPTION
PIN
15
NAME
DESCRIPTION
No Connection(1)
No Connection(1)
No connection(1)
Ground
N/C
N/C
N/C
2
VATTN
Supply for Attenuator
16
3
ATTIN (+) Attenuator (+) Input (2)
17
Ground for Digital
CMOS Circuit
4
A1OUT (+) Amplifier A1 (+) Output
18
GNDCMOS
5
6
A1IN (+)
Vg1
Amplifier A1 (+) Input (2)
Amplifier A1 (+/-) Control
19
20
ATTOUT (-) Attenuator (-) Output (2)
A2IN (-)
Amplifier A2 (-) Input (2)
Amplifier A1 (+/-) Current
Adjust
7
8
ISET1
21
22
A2OUT (-)
Amplifier A2 (-) Output
Amplifier A2 (+/-)
Current Adjust
A1IN (-)
Amplifier A1 (-) Input (2)
ISET2
Vg2
9
A1OUT (-)
ATTIN (-)
Amplifier A1 (-) Output
Attenuator (-) Input (2)
23
24
Amplifier A2 (+/-) Control
10
A2 OUT (+) Amplifier A2 (+) Output
A2 IN (+)
Amplifier A2 (+) Input (2)
ATTOUT (+) Attenuator (+) Output (2)
Supply For Digital
CMOS Circuit
11
VCMOS
25
12
13
CLK
DAT
En
Clock
Data
26
27
28
N/C
No Connection(1)
Ground
14
Enable
GND
Notes:
(1) All N/C pins should be grounded.
(2) Pins should be AC-coupled. No external DC bias should be applied.
Data Sheet - Rev 2.1
07/2005
3
ANADIGICS [ ANADIGICS, INC ]
