AIT1042
Table 6: Digital 2-Wire Interface Specifications
(T = +55 °C, VDD = +5.0 V, ref. Figure 3)
C
PARAMETER
SYMBOL
MIN
MAX
400
-
UNIT
kHz
V
CLKꢀFrequency
fCLK
1
LogicꢀHighꢀInputꢀ(pinsꢀ23,ꢀ24)
V
H
2.0
LogicꢀLowꢀInputꢀ(pinsꢀ23,ꢀ24)
V
L
-
-
-
-
0.8
10
V
A
A
LogicꢀInputꢀCurrentꢀConsumptionꢀ(pinsꢀ23,ꢀ24)
AddressꢀSelectꢀInputꢀCurrentꢀConsumtionꢀ(pinꢀ25)
DataꢀSinkꢀCurrentꢀ(2)
ILOG
IAS
10
IAK
4.0
mA
BusꢀFreeꢀTimeꢀbetweenꢀaꢀSTOPꢀandꢀSTART
Condition
s
t
BUF
1.3
0.6
-
-
HoldꢀTimeꢀ(repeated)ꢀSTARTꢀꢀCondition.ꢀAfterꢀthis
period,ꢀtheꢀfirstꢀclockꢀpulseꢀisꢀgenerated.
s
t
HD;STA
s
s
s
s
LOWꢀperiodꢀofꢀCLK
t
LOW
1.3
0.6
-
-
HIGHꢀperiodꢀofꢀCLK
tHIGH
Set-upꢀTimeꢀforꢀaꢀRepeatedꢀSTARTꢀCondition
DataꢀHoldꢀTimeꢀ(forꢀ2-wireꢀbusꢀdevices)
DataꢀSet-upꢀTime
t
SU;STA
0.6
-
t
HD;DAT
0.0
0.9
-
t
SU;DAT
100
ns
ns
ns
s
(1)
(1)
RiseꢀTimeꢀofꢀDATAꢀandꢀCLKꢀsignals
FallꢀTimeꢀofꢀDataꢀandꢀCLKꢀsignals
Set-upꢀTimeꢀforꢀSTOPꢀCondition
CapacitiveꢀLoadꢀforꢀEachꢀBusꢀLine
tR
20ꢀ+ꢀ0.1C
20ꢀ+ꢀ0.1C
0.6
b
b
300
300
-
tF
t
SU;STO
C
b
-
400
pF
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum VH and maximum VL levels.
DATA
t
F
t
LOW
t
R
t
SU;DAT
t
F
t
HD;STA
t
SP
t
R
tBUF
CLK
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
tSU;STO
S
Sr
P
S
Figure 3: Serial 2-Wire Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.0
6
02/2009
ANADIGICS [ ANADIGICS, INC ]
