ACD2202
Programmable Modes
Each register contains bits set aside for
programming different modes of operation in the
synthesizers. Currently, the only programmable
mode is the polarity of the phase detector in each of
the synthesizers. Bit D1 in each reference divider
register controls this feature. Bits D2 through D5 in
the reference divider registers and bits C1 and C2
in the main divider registers are reserved for future
use, and have no current function. They can be set
either high or low without affecting synthesizer
performance.
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 21.
Figure 21: VCO Characteristics
Table 14: Phase Detector Polarity Bit
S
2
S
1
D
1
(1)
0
1
0
0
PLL2 Phase Detector Polarity
PLL1 Phase Detector Polarity
VCO OUTPUT
FREQUENCY
Table 15: Phase Detector Polarity Selection
PHASE
VCO
D
1
DETECTOR
POLARITY
CHARACTERISTICS
(SEE FIGURE 12)
(2)
0
1
Negative
Positive
curve (2)
curve (1)
VCO INPUT VOLTAGE
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2202 details the calculations
used to determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = fOSC / fPD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are RPLL2 = 000000001000000.
Data Sheet - Rev 2.1
12/2003
13
ANADIGICS [ ANADIGICS, INC ]
