AS1916 - AS1918
austriam
i c r o
systems
RESET/RESETN
Data Sheet
8 Detailed Description
The AS1916 - AS1918 supervisory circuits were designed to generate a reset when the monitored supply voltage falls
below its factory-trimmed trip threshold (see V
TH
on
and to maintain the reset for a minimum timeout period
(see t
RP
on
after the supply has stabilized.
The integrated watchdog timer
helps mitigate against bad programming code or clock
signals, and/or poor peripheral response.
The active-low manual reset input
allows for an externally activated system reset.
RESET/RESETN
Whenever the monitored supply voltage falls below its reset threshold, the RESET output asserts low or the RESETN
output asserts high. Once the monitored voltage has stabilized, an internal timer keeps the reset asserted for the reset
timeout period (t
RP
). After the t
RP
period, the RESET/RESETN output returns to its original state
Figure 9. Functional Diagram of V
CC
Supervisory Application
5
V
CC
AS1916 - AS1918
Reset Timeout
Delay Generator
1
RESETN/
RESET
+
–
1.26V
V
CC
3
MRN
4
WDI
Watchdog Transition
Detector
Watchdog
Timer
2
GND
Figure 10. Reset Timing Diagram
V
CC
1V
V
TH
V
TH
1V
RESETN
t
RP
t
RD
RESET
GND
t
RP
t
RD
www.austriamicrosystems.com
Revision 0.52
7 - 13