AS1916 - AS1918
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1916 - AS1918 supervisory circuits were designed to generate a reset when the monitored supply voltage falls below its factory-trimmed
trip threshold (see V
TH
on
and to maintain the reset for a minimum timeout period (see t
RP
on
after the supply has stabilized.
The integrated watchdog timer
helps mitigate against bad programming code or clock signals, and/or poor
peripheral response.
The active-low manual reset input
allows for an externally activated system reset.
8.1 RESET/RESETN
VCC
MRN
WDI
Figure 10. Reset Timing Diagram
Te
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AS1916 - AS1918
Reset Timeout Delay
Generator
+
–
1.26V
V
CC
3
4
Watchdog Transition
Detector
Watchdog
Timer
VCC
1V
V
TH
V
TH
RESETN
t
RP
t
RD
RESET
GND
t
RP
t
RD
Revision 1.04
lv
1
RESETN/
RESET
2
GND
1V
Figure 9. Functional Diagram of V
CC
Supervisory Application
al
7 - 14
Whenever the monitored supply voltage falls below its reset threshold, the RESET output asserts low or the RESETN output asserts high. Once
the monitored voltage has stabilized, an internal timer keeps the reset asserted for the reset timeout period (t
RP
). After the t
RP
period, the
RESET/RESETN output returns to its original state
id
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
