AS1545
Datasheet - Detailed Description
Analog-to-Digital Conversion
The analog inputs of the AS1545 can be configured as single-ended pseudo-differential or fully differential via the SGL/
DIFF logic pin, as shown in Figure 41. If this pin is coupled to a logic low, the analog input channels to each on-chip
ADC are set up as three fully differential pairs or 3 pseudo-differential inputs. If this pin is at logic high, the analog input
channels to each on-chip ADC are set up as six single-ended analog inputs. The required logic level on this pin needs
to be established prior to the acquisition time and remain unchanged during the conversion time until the track-and-
hold has returned to track. The track-and-hold returns to track on the 13th rising edge of SCLK after the CSN falling
edge (see Figure 51). If the level on this pin is changed, it is recognized by the AS1545; therefore, keep the same logic
level during acquisition and conversion to avoid corrupting the conversion in progress.
The channels used for simultaneous conversions are selected via the multiplexer address input pins, A0 to A2. The
logic states of these pins also need to be established prior to the acquisition time; however, they may change during
the conversion time, provided that the mode is not changed. If the mode is changed from fully differential to pseudo-
differential, for example, then the acquisition time would start again from this point. The selected input channels are
decoded as shown in Table 5 on page 20.
The analog input range of the AS1545 can be selected as [0V to VREF or -VREF/2 to +VREF/2] or [0V to 2×VREF or
-VREF to +VREF] via the RANGE and MODE pin (see Table 5 on page 20). This selection is made in a similar fashion to
that of the SGL/DIFF pin by setting the logic state of the RANGE pin a time tACQ prior to the falling edge of CSN. The
logic level on this pin can be altered after the third falling edge of SCLK. If this pin is tied to a logic low, the analog input
range selected is [0V to VREF or -VREF/2 to +VREF/2]. If this pin is tied to a logic high, the analog input range selected is
[0V to 2×VREF or -VREF to +VREF].
Figure 41. Selecting Differential or Singe-Ended Configuration
A
B
CSN
tACQ
14
1
1
14
SCLK
SGL/
DIFF
Output Coding
The AS1545 output coding is set to either twos complement or straight binary, depending on which analog input
configuration is selected for a conversion. Output coding scheme for each possible analog input configuration is show
in the Table 7.
Table 7. AS1545 Output Coding
MODE
Differential
Output Coding
Twos complement
Straight binary
Single-Ended
Pseudo-Differential
Straight binary
Transfer Functions
The designed code transitions occur at successive integer LSB values (1 LSB, 2 LSB, and so on). In single-ended
mode, the LSB size is VREF/4096 when the 0V to VREF range is used, and the LSB size is 2 × VREF/4096 when the 0V
to 2 × VREF range is used. In differential mode, the LSB size is 2 × VREF/4096 when the 0V to VREF. The ideal transfer
characteristic for the AS1545 when straight binary coding is output is shown (with the 2 × VREF range) in Figure 42 &
Figure 43 on page 24, and Figure 44 & Figure 45 on page 24 shows the twos complement.
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