AS1543/44
Data Sheet - Electrical Characteristics
Timing Specifications
VDD = 2.7 to 5.25V, VDRIVE ≤ VDD, REFIN = 2.5V; TAMB = -40 to +85°C (unless otherwise specified). Specifications
based on load circuit shown in Figure 3 on page 8.
Table 4.
Symbol
fSCLK
tCP
Min
0.01
50
Typ
Max
Unit
MHz
ns
Description
SCLK frequency
SCLK periode
20
Minimum quiet time required between bus relinquish and next
conversion start.
tQUIET
50
10
ns
CSN Fall to SCLK Fall Setup
CSN Fall to DOUT Enabled.
CSN Fall to DOUT Valid.
tCSS
tCSDOE
tCSDOV
tCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
20
40
SCLK Pulse Width Low.
0.4 tCP
0.4 tCP
10
SCLK Pulse Width High.
tCH
SCLK Fall to DOUT Hold.
tDOH
tDOV
tDOD
tDS
SCLK Fall to DOUT Valid.
SCLK Fall to DOUT Disable.
DIN to SCLK Fall Setup.
50
50
15
20
5
DIN to SCLK Fall Hold.
tDH
Sixteenth SCLK Fall to CSN Rise Hold.
Power-up time from auto shutdown mode.
tCSH
20
tWAKEUP
1
Figure 3. Load Circuit for Digital Output Timing Specifications
200µA
IOL
VDD/2
DOUT
CLOAD
25pF
200µA
IOH
Figure 4. Serial Interface Timing Diagram
CSN
tCONVERT
B
tCSS
SCLK
tCH
12
13
14
15
16
1
2
3
4
5
6
tCSH
tCSDOV
tCSDOE
tDOV
tDOH
tCL
tQUIET
DOUT
ADDR2 ADDR1 ADDR0
DB11
DB10
tDH
ADDR3 ADDR2 ADDR1 ADDR0
DB3
DB2
DB1
DB0
Tri-State
Tri-State
ADDR3
4 ID Bits
tDOD
tDS
DIN
SEQ
SE/FDN
DC
DC
DC
WRITE
DC = Don’t Care
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