AS1543/44
Data Sheet - Detailed Description
Channel Counter Conversion (SEQ = 1, SHADOW = 1)
Figure 30 shows how a sequence of consecutive channels can be converted from without having to program the
shadow register or write to the part on each serial transfer. To exit this mode of operation and revert back to the normal
mode of operation of a multi-channel ADC (as outlined in Figure 29), verify bit WRITE (page 14) = 1 and bits SEQ and
SHADOW = 0 on the next serial transfer.
Figure 30. Bit SEQ = 1, Bit SHADOW = 1 Flowchart
Power On
DOUT: Dummy Conversion Result
DIN: Write to Control Register;
Bit WRITE = 1;
Select Coding, Range, SE/FDN,
WEAK/TRIN and Power Mode
CSN Falling
Edge
*The binary selected channel number
will determine the last channel used for
conversion. e.g.: 0101 = 5 => channel
0:5 will be used for conversion.
Use ADDR3:ADDR0 (see Table 5 on page 14)
for Channel Counter Conversion*
Bit SEQ = 1, Bit SHADOW = 1
Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0
Bit WRITE = 0
Bit WRITE = 0
Bit WRITE = 1
Bit SEQ = 1
Bit SHADOW = 0
DOUT: Conversion Result from previously
selected Channel
DOUT: Conversion Result from pre-
viously selected Channel
Bit WRITE = 1,
Bit SEQ = 1,
Bit SHADOW = 0
Bit WRITE = 0
Continuously Convert Consecutive
Sequence of
Continuously Convert the Selected
Sequence of
Channels from Channel 0 up to and includ-
ing Previously
Selected ADDR3:ADDR0 in the Control
Register
Channels and Allow Changes to
Control Register
without Conversion Interruption
CSN Falling
Edge
CSN Falling
Edge
Exit this flow whenever WRITE = 1 and NOT (SEQ = 1, SHADOW = 0)
Serial Interface
Figure 31 shows the detailed timing diagram for serial interfacing to the AS1543/44. The serial clock provides the con-
version clock and also controls the transfer of information to and from the AS1543/44 during each conversion.
Figure 31. Serial Interface Timing Diagram
CSN
tCONVERT
B
tCSS
SCLK
tCH
12
13
14
15
16
1
2
3
4
5
6
tCSH
tCSDOV
tCSDOE
tDOV
tDOH
tCL
tQUIET
DOUT
ADDR2 ADDR1 ADDR0
DB11
DB10
tDH
ADDR3 ADDR2 ADDR1 ADDR0
DB3
DB2
DB1
DB0
Tri-State
Tri-State
ADDR3
4 ID Bits
tDOD
tDS
DIN
SEQ
SE/FDN
DC
DC
DC
WRITE
DC = Don’t Care
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