欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS1544-BTST 参数 Datasheet PDF下载

AS1544-BTST图片预览
型号: AS1544-BTST
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4通道, 1 MSPS , 12位ADC,序 [8/4-Channel, 1 Msps, 12-Bit ADC with Sequencer]
分类和应用:
文件页数/大小: 29 页 / 1031 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号AS1544-BTST的Datasheet PDF文件第13页浏览型号AS1544-BTST的Datasheet PDF文件第14页浏览型号AS1544-BTST的Datasheet PDF文件第15页浏览型号AS1544-BTST的Datasheet PDF文件第16页浏览型号AS1544-BTST的Datasheet PDF文件第18页浏览型号AS1544-BTST的Datasheet PDF文件第19页浏览型号AS1544-BTST的Datasheet PDF文件第20页浏览型号AS1544-BTST的Datasheet PDF文件第21页  
AS1543/44  
Data Sheet - Detailed Description  
Power Mode Selection  
Control register bits PM1 and PM0 are used to configure the AS1543/44 power mode.  
Table 10. Power Mode Selection via Bits PM1 and PM0  
PM1  
PM0  
Mode  
Description  
In this mode, the AS1543/44 remains in full power mode regardless of the  
status of any of the logic inputs. This mode allows the fastest possible  
throughput rate.  
1
1
Normal Operation  
In this mode, the AS1543/44 automatically enters shutdown mode at the end of  
each conversion when the control register is updated. Wake-up time from  
shutdown is 1µs.  
0
X
Auto Shutdown  
Note: Ensure that 1µs has elapsed before attempting to perform a valid conver-  
sion in this mode.  
Sequencer Operation  
The setting of control register bits SEQ and SHADOW sets the sequencer operation and also selects the shadow reg-  
ister for programming.  
Table 11. Sequencer Configuration via Bits SEQ and SHADOW  
SEQ  
SHADOW  
Description  
These settings indicate that the sequencer is not used. The analog input  
channel selected for each individual conversion is determined by the  
contents of the channel address bits ADDR3:ADDR0 (page 14) in each  
prior write operation. This mode of operation reflects the normal operation  
of a multi-channel ADC (without the sequencer) where each write to the  
AS1543/44 specifies the next input channel for conversion (see Figure 28  
on page 18).  
0
0
These settings select the shadow register for programming. After a write  
to the control register, the following write operation will load the contents  
of the shadow register. This will program the sequence of channels to be  
repeatedly converted each successive valid CSN falling edge (see  
Table 12 on page 18 and Figure 29 on page 19).  
0
1
Note: The specified input channels need not be consecutive.  
With these settings, the sequencer will not be interrupted upon  
completion of a write operation. This allows other bits of the control  
register (PM1, PM0, WEAK/TRIN, RANGE, CODING and SE/FDN) to be  
altered while in a sequence without terminating the cycle.  
1
1
0
1
These settings are used in conjunction with the channel address bits  
ADDR3:ADDR0 to program continuous conversions on a consecutive  
sequence of channels (channel 0 ... channel n) as determined by the  
address bits ADDR3:ADDR0 (page 14) of the control register (see Figure  
30 on page 20).  
www.austriamicrosystems.com  
Revision 1.00  
17 - 29  
 复制成功!