AS1543/44
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Specifications
V
DD
= 2.7 to 5.25V, VDRIVE
≤
V
DD
, REFIN = 2.5V; T
AMB
= -40 to +85°C (unless otherwise specified). Specifications
based on load circuit shown in
Table 4.
Symbol
f
SCLK
t
CP
t
QUIET
t
CSS
t
CSDOE
t
CSDOV
t
CL
t
CH
t
DOH
t
DOV
t
DOD
t
DS
t
DH
t
CSH
t
WAKEUP
15
20
5
20
1
0.4 t
CP
0.4 t
CP
10
50
50
Min
0.01
50
50
10
20
40
Typ
Max
20
Unit
MHz SCLK frequency
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK periode
Minimum quiet time required between bus relinquish and next
conversion start.
CSN Fall to SCLK Fall Setup
CSN Fall to DOUT Enabled.
CSN Fall to DOUT Valid.
SCLK Pulse Width Low.
SCLK Pulse Width High.
SCLK Fall to DOUT Hold.
SCLK Fall to DOUT Valid.
SCLK Fall to DOUT Disable.
DIN to SCLK Fall Setup.
DIN to SCLK Fall Hold.
Sixteenth SCLK Fall to CSN Rise Hold.
Power-up time from auto shutdown mode.
Description
Figure 3. Load Circuit for Digital Output Timing Specifications
200µA
I
OL
DOUT
C
LOAD
25pF
200µA
I
OH
VDD/2
Figure 4. Serial Interface Timing Diagram
CSN
t
CONVERT
SCLK
t
CSS
t
CH
1
t
CSDOV
t
CSDOE
DOUT
Tri-State
ADDR3
DIN
ADDR2
t
DS
WRITE
SEQ
ADDR1
ADDR0
4 ID Bits
ADDR3
ADDR2
2
3
4
t
DOV
DB11
DB10
t
DH
ADDR1
ADDR0
SE/FDN
5
6
t
DOH
DB3
DB2
12
13
B
14
t
CL
DB1
DB0
t
DOD
DC
DC
DC
DC = Don’t Care
15
16
t
CSH
t
QUIET
Tri-State
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