AS1538/AS1540
Data Sheet - Detailed Description
8 Detailed Description
The AS1538/AS1540 successive approximation register (SAR) A/D converter architecture is based on capacitive
redistribution which inherently includes a sample-and- hold function.
The AS1538/AS1540 core is controlled by an internally generated free-running clock. When the device is not perform-
ing conversions or being addressed, the A/D converter-core and internal clock are powered off.
Figure 22. Simplified I/O Diagram
+2.7 to
+5.25V
+
0.1 to
10µF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
VDD
+
0.1 to
10µF
2kΩ
SDA
SCL
AS1538/
AS1540
Microcontroller
A0
A1
COM
GND
REFIN/OUT
1µF
Analog Input
When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal capacitor
array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period,
the source must charge the internal sampling capacitor (typically 15pF). After the capacitor has been fully charged,
there is no further input current. The amount of charge transfer from the analog source to the converter is a function of
conversion rate.
Figure 23. Reference circuit
VIN
+2.7 to
+5.25V
+
-
10Ω
CH0:CH7
REFIN/OUT
VDD
+
0.1 to
10µF
1nF
2kΩ
AS1538
SDA
1µF
www.austriamicrosystems.com
Revision 1.03
10 - 20
AMSCO [ AMS(艾迈斯) ]
