欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS1537-BSOU 参数 Datasheet PDF下载

AS1537-BSOU图片预览
型号: AS1537-BSOU
PDF下载: 下载PDF文件 查看货源
内容描述: 12位,单电源,低功耗, 73ksps A / D转换器 [12-Bit, Single Supply, Low-Power, 73ksps A/D Converters]
分类和应用: 转换器
文件页数/大小: 21 页 / 782 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号AS1537-BSOU的Datasheet PDF文件第2页浏览型号AS1537-BSOU的Datasheet PDF文件第3页浏览型号AS1537-BSOU的Datasheet PDF文件第4页浏览型号AS1537-BSOU的Datasheet PDF文件第5页浏览型号AS1537-BSOU的Datasheet PDF文件第7页浏览型号AS1537-BSOU的Datasheet PDF文件第8页浏览型号AS1537-BSOU的Datasheet PDF文件第9页浏览型号AS1537-BSOU的Datasheet PDF文件第10页  
AS1536/AS1537  
Datasheet - Electrical Characteristics  
Table 3. Electrical Characteristics (Continued)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Digital Inputs: SCLK, SHDNN, CSN  
0.7x  
VDD  
VIH  
VIL  
SCLK, CSN Input High Voltage  
SCLK, CSN Input Low Voltage  
V
V
0.3x  
VDD  
VHYST  
IIN  
SCLK, CSN Input Hysteresis  
SCLK, CSN Input Leakage  
0.2  
V
VIN = 0V or VDD  
±0.01  
±1  
15  
µA  
SCLK, CSN Input Capacitance 7  
CIN  
pF  
V
VDD -  
0.4  
VSH  
VSL  
SHDNN Input High Voltage  
SHDNN Input Low Voltage  
SHDNN Input Current  
0.4  
V
SHDNN = 0V or VDD  
±4.0  
µA  
VDD -  
1.1  
VSM  
VFLT  
SHDNN Input Mid Voltage  
SHDNN Voltage, Floating  
1.1  
V
V
SHDNN = float  
SHDNN = float  
VDD/2  
SHDNN Max Allowed Leakage,  
Mid Input  
±50  
nA  
Digital Output: DOUT  
ISINK = 5mA  
0.4  
0.8  
VOL  
VOH  
Output Voltage Low  
V
V
ISINK = 16mA  
VDD -  
0.5  
Output Voltage High  
ISOURCE = 0.5mA  
CSN = VDD  
IL  
Tri-State Leakage Current  
±0.01 ±10  
15  
µA  
pF  
7
COUT  
Tri-State Output Capacitance  
CSN = VDD  
Power Requirements  
VDD  
IDD  
Supply Voltage  
2.7  
5.25  
V
Int. Reference (AS1536), VDD = 3.6V  
Int. Reference (AS1536), VDD = 5.25V  
External Reference, VDD = 3.6V  
External Reference, VDD = 5.25V  
Shutdown mode, VDD = 3.6V  
1.4  
1.6  
1.0  
1.2  
0.3  
0.6  
2.0  
2.3  
1.4  
1.7  
2
mA  
Supply Current  
µA  
Shutdown mode, VDD = 5.25V  
4
VDD = VDDMIN to VDDMAX,  
full-scale input  
Power-Supply Rejection 8  
PSR  
±1  
mV  
1. Tested at VDD = +2.7V.  
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale  
range and offset have been calibrated.  
3. Offset nulled.  
4. Achievable with standard timing (see Figure 25 on page 14).  
5. Sample tested at 0.1% AQL.  
6. External load should not change during conversion for specified accuracy.  
7. Guaranteed by design; not subject to production testing.  
8. Measured as [VFS(VDDMIN) - VFS(VDDMAX)] with external reference.  
www.austriamicrosystems.com  
Revision 1.01  
7 - 22  
 复制成功!