AS1528/AS1529
Datasheet - Application Information
Figure 23. Microwire Serial Interface Connections
8
SK
I/O
SCLK
AS1528/
AS1529
6
CPU
CNVST
7
SI
DOUT
Figure 24. SPI/Microwire Interface Timing Diagram (CPOL = CPHA = 0)
Sampling Instant
1st Byte Read
CNVST
2nd Byte Read
1
4
8
12
16
SCLK
DOUT
High Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B3
B2
B1
ZERO
ZERO
B4
QSPI Interface
Using the high-speed QSPI interface (Figure 25) with CPOL = 0 and CPHA = 0, the AS1528/AS1529 support a maxi-
mum fSCLK of 8MHz. One 12- to 16-bit reads are necessary to obtain the entire 10-bit result from the AS1528/AS1529.
DOUT data transitions on the serial clock’s falling edge and is clocked into the processor on SCLK’s rising edge. The
first 10 bits are the data. DOUT then goes high impedance (see Figure 23).
Figure 25. QSPI Serial Interface Connections
8
SCK
CSM
SCLK
6
AS1528/
AS1529
CPU
CNVST
SSM
7
MISO
DOUT
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