AS1520/AS1521
Data Sheet - Application Information
Quick Evaluation Circuit
In order to quickly evaluate the analog performance of the AS1520/AS1521, use the circuit shown in Figure 35.
Figure 35. Evaluation Circuit Diagram
+3 or
+5V
20
VDD1
19
VDD2
10
0.1µF
10µF
VDD3
+2.5V
Analog
Input
8
13
GND
CH7
17
0.1µF
AS1520/
AS1521
CSN
TBA
18
External
Clock
9
SCLK
16
COM
To
VDD2
DIN
14
11
REF
DOUT
12
15
REFADJ
SSTRB
4.7µF
0.1µF
Connecting DIN to VDD2 shifts in control bytes of $FFh, which trigger single-ended conversions (bit RANGE (page 15)
= 1) on CH7 without powering down between conversions. The SSTRB output pulses high for one clock period before
the MSB of the 10-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence
of bits from DOUT. A total of 16 clock cycles is required per conversion.
Note: All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK.
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