AS1504, AS1505
austriamicrosystems
Data Sheet
Supply Bypassing
9 Application Information
Supply Bypassing
The AS1504/AS1505 require a well-filtered power source. In most applications, the AS1504/AS1505 should be pow-
ered directly from the system power supply (+3 to +5V). However, if the logic supply is a switch-mode design, it will
probably generate noise in the 20kHz to 1MHz range. Additionally, fast logic gates can generate transients hundred of
millivolts in amplitude from wiring resistance and inductance.
The circuit shown in Figure 18 isolates the analog section from any logic switching transients. Even if a separate power
supply trace is not available, adequate supply bypassing will reduce supply-line induced errors. Local supply bypass-
ing consisting of a 10µF tantalum electrolytic capacitor in parallel with a 0.1µF ceramic capacitor is recommended (see
Figure 19).
Figure 18. Power Supply Traces
CMOS/TTL
Logic Circuits
AS1504/
AS1505
10µF
Tantalum
+
0.1µF
+5V Power
Supply
Figure 19. Recommended Supply Bypassing
+5V
16 VDD
10µF
Tantalum
+
AS1504/
AS1505
0.1µF
8
GND
Output Buffering
For most designs, the nominal 5kΩ output impedance of the AS1504/AS1505 is sufficient to drive succeeding circuitry.
If a lower output impedance is required, an external amplifier can be added (see Figure 20 on page 13).
A single amplifier should be used as a simple buffer to reduce the output resistance of DAC1. An amplifier with low off-
set voltage, low supply current, and operation at less than 3V is recommended due to its rail-to-rail input and output
operation. DAC2 and DAC3 are configured in a summing arrangement where DAC3 provides the coarse output volt-
age setting and DAC2 is used for fine adjustments.
The use of R1 in series with DAC2 (see Figure 20 on page 13)attenuates its contribution to the voltage sum node at the
output of DAC3.
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