AS1504, AS1505
austriamicrosystems
Data Sheet
Programming The Output Voltage
Figure 15. Equivalent DAC Circuit
To other DACs
P CH
N CH
VREFH
MSB
2R
2R
Ox
R
DAC
Register
D7
D6
D0
R
2R
2R
LSB
GND
VREFL
Programming The Output Voltage
The output voltage range is determined by the external reference connected to pins VREFH and VREFL (see Figure 15
on page 10 for a simplified diagram of the equivalent DAC circuit).
VREFL for the AS1504 is internally connected to GND and therefore cannot be offset. Pin VREFH can be tied to VDD and
pin VREFL can be tied to GND establishing a basic rail-to-rail output voltage programming range. Other output ranges
are established by the use of different external voltage references.
The programmed output voltage is determined as:
VOUT (Dx) = (Dx)/256 x (VREFH – VREFL) + VREFL
(EQ 2)
Where:
Dx is the data contained in the 8-bit DACx latch.
For example, when VREFH = +5V and VREFL = 0V the output voltages will be generated per the codes listed in Table 6.
Table 6. Output Voltages
Data Bits
VOUTx
4.98V
2.50V
0.02V
0.00V
Output State (VREFH = +5V, VREFL = 0V)
255
128
1
Full-Scale
Half-Scale (Mid-Scale Reset Value)
1 LSB
0
Zero-Scale
Reference Inputs
The reference input pins (VREFH and VREFL) set the output voltage range of all eight DACs. For the AS1504, only pin
VREFH is available to establish a programmable full-scale output voltage.
Note: The external reference voltage can be any value between 0 and VDD but must not exceed VDD.
The AS1505 uses pin VREFL to establish the zero-scale output voltage. Any voltage can be applied between 0 and
VDD. VREFL can be smaller or larger than VREFH since the DAC design uses fully bi-directional switches as shown in
Figure 15. The input resistance to the DAC has a code dependent variation that has a nominal worst case measured at
55h, which is approximately 2kΩ. When VREFH is greater than VREFL, the REFL reference must be able to sink current
out of the DAC ladder, while the REFH reference is sourcing current into the DAC ladder. The DAC design minimizes
reference glitch current, thus maintaining minimum interference between DAC channels during code changes.
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